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LPC47M192
LPC Super I/O with Hardware Monitoring Block
FEATURES
3.3 Volt Operation (SIO Block is 5 Volt Tolerant) LPC Interface ACPI 1.0/2.0 Compliant Fan Control Fan Speed Control Outputs (2) Fan Tachometer Inputs (2) Programmable Wake-up Event Interface PC98, PC99, PC01 Compliant Dual Game Port Interface MPU-401 MIDI Support General Purpose Input/Output Pins (37) ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management System Management Interrupt 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports Two Floppy Drives Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to 15 IRQ and Three DMA Options Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Keyboard Controller 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer
SMSC DS - LPC47M192
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Port 92 Support Fast Gate A20 and KRESET Outputs Serial Ports Two Full Function Serial Ports High Speed 16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options Infrared Port Multiprotocol Infrared Interface IrDA 1.0 Compliant SHARP ASK IR 480 Addresses, Up to 15 IRQ Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bi-directional Parallel Port Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection 960 Address, Up to 15 IRQ and Three DMA Options LPC Interface Multiplexed Command, Address and Data Bus Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PME Interface Hardware Monitor Monitor Power supplies (+2.5V, +3.3V, +5V, +12V, +1.8V, +1.5V, Vccp (processor voltage), and VCC or HVSB) Remote Thermal Diode Sensing for Two External Temperature Measurements Internal Ambient Temperature Measurement Limit Comparison of all Monitored Values System Management Bus (SMBus) Interface THERM# Pin for out-of-limit Temperature or Voltage Indication RESET# Pin for generating 20msec Low Reset Pulse Configurable offset for internal or external temperature channels. AMI Keyboard BIOS ROM 128 Pin QFP, 3.2mm footprint Package; green, lead-free package also available
Rev. 03/30/05
DATASHEET
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) SMSC 2005. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS - LPC47M192
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Rev. 03/30/05
DATASHEET
1
GENERAL DESCRIPTION
The LPC47M192 is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller with an LPC interface and Hardware Monitoring capabilities. The LPC47M192's hardware monitoring capability includes voltage and temperature monitoring with the ability to alert the system of out-of-limit conditions. There are 7 analog inputs for monitoring external voltages of +1.5V, +1.8V, +2.5V, +3.3V, +5V, +12V and Vccp (core processor voltage), as well as internal monitoring of the devices own HVCC or HVSB. The LPC47M192 includes support for monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. The nTHERM pin is implemented to indicate out-of-limit temperature and voltage conditions. The block has an ability to output 20ms low pulse via nRESET pin. The hardware monitoring block of the LPC47M192 is accessible via the System Management Bus (SMBus). The LPC47M192 incorporates complete legacy Super I/O functionality including an 8042 based keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, two serial ports that are 16C550A UART compatible, two IrDA 1.0 infrared ports, and a floppy disk controller with SMSC's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with SMSC's proprietary 82077AA core. System related functionality, which offers flexibility to the system designer, includes an MPU-401 MIDI interface, (37) General Purpose I/O control functions, control of two LED's, a game port interface supporting two joysticks, and fan control using fan tachometer inputs and pulse width modulator, (PWM), outputs The LPC47M192 is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events. The LPC47M192 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M192 may be reprogrammed through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address location options, a Serialized IRQ interface, and Three DMA channels. The LPC47M192 does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area.
ORDERING INFORMATION PART# LPC47M192-NC LPC47M192-NW PACKAGE 128 Pin QFP 128 Pin QFP Green, Lead-Free KEYBOARD BIOS AMI AMI
SMSC DS - LPC47M192
Page 3
Rev. 03/30/05
DATASHEET
TABLE OF CONTENTS
1 2 3 4 GENERAL DESCRIPTION .................................................................................................................... 3 PIN LAYOUT ........................................................................................................................................ 10 PIN CONFIGURATION ........................................................................................................................ 11 DESCRIPTION OF PIN FUNCTIONS.................................................................................................. 12 4.1 4.2 BUFFER NAME DESCRIPTIONS........................................................................................................... 20 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS.......................................................................... 20
Super I/O Pins ........................................................................................................................................20 Hardware Monitoring Block Pins.............................................................................................................21
4.2.1 4.2.2
5 6
BLOCK DIAGRAM............................................................................................................................... 22 POWER FUNCTIONALITY .................................................................................................................. 23 6.1 6.2 6.3 6.4 6.5 6.6 6.7 VCC/HVCC POWER ........................................................................................................................ 23
3 VOLT OPERATION / 5 VOLT TOLERANCE .......................................................................................23 6.1.1
VREF PIN........................................................................................................................................ 23 VTR SUPPORT................................................................................................................................. 23
Trickle Power Functionality .....................................................................................................................23 Indication of 32KHZ Clock ......................................................................................................................25
6.3.1 6.4.1
32.768 KHZ TRICKLE CLOCK INPUT................................................................................................... 25 INTERNAL PWRGOOD..................................................................................................................... 25 MAXIMUM CURRENT VALUES............................................................................................................. 25
Super I/O Functions................................................................................................................................25 Hardware Monitoring Block Functions ....................................................................................................26
6.6.1 6.6.2
POWER MANAGEMENT EVENTS (PME/SCI)....................................................................................... 26 SUPER I/O REGISTERS ..................................................................................................................... 27 HOST PROCESSOR INTERFACE (LPC) ............................................................................................... 27 LPC INTERFACE ...............................................................................................................................28
7
FUNCTIONAL DESCRIPTION............................................................................................................. 27 7.1 7.2 7.3
7.3.1 LPC Interface Signal Definition...............................................................................................................28 7.3.2 LPC Cycles .............................................................................................................................................28 7.3.3 Field Definitions ......................................................................................................................................28 7.3.4 LFRAME# Usage....................................................................................................................................28 7.3.5 I/O Read and Write Cycles .....................................................................................................................29 7.3.6 DMA Read and Write Cycles ..................................................................................................................29 7.3.7 DMA Protocol .........................................................................................................................................29 7.3.8 POWER MANAGEMENT .......................................................................................................................29 7.3.8.1 CLOCKRUN Protocol .................................................................................................................................... 29 7.3.8.2 LPCPD Protocol.............................................................................................................................................. 29 7.3.9 SYNC Protocol .......................................................................................................................................29 7.3.9.1 Typical Usage ................................................................................................................................................. 29 7.3.9.2 SYNC Timeout ............................................................................................................................................... 30 7.3.9.3 SYNC Patterns and Maximum Number of SYNCS ........................................................................................ 30 7.3.9.4 SYNC Error Indication.................................................................................................................................... 30 7.3.9.5 I/O and DMA START Fields .......................................................................................................................... 30 7.3.9.6 Reset Policy..................................................................................................................................................... 30 7.3.10 LPC TRANSFERS ..............................................................................................................................30 7.3.10.1 Wait State Requirements................................................................................................................................. 30
7.4
FLOPPY DISK CONTROLLER .............................................................................................................. 31
FDC Internal Registers ...........................................................................................................................31 STATUS REGISTER ENCODING ..........................................................................................................41 Instruction Set.........................................................................................................................................48 DATA TRANSFER COMMANDS............................................................................................................54 DIRECT SUPPORT FOR TWO FLOPPY DRIVES.................................................................................64
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7.4.1 7.4.2 7.4.3 7.4.4 7.4.5
SMSC DS - LPC47M192
DATASHEET
7.4.6
FDC Swap Bit .........................................................................................................................................64
7.5 7.6 7.7
SERIAL PORT (UART)................................................................................................................... 64 INFRARED INTERFACE................................................................................................................ 77 MPU-401 MIDI UART ..................................................................................................................... 78
7.7.1 Overview.................................................................................................................................................78 7.7.2 Host Interface .........................................................................................................................................79 7.7.3 MIDI Data Port ........................................................................................................................................79 7.7.4 Status Port..............................................................................................................................................79 7.7.4.1 Bit 7 - MIDI Receive Buffer Empty ............................................................................................................... 79 7.7.4.2 Bit 6 - MIDI Transmit Busy ........................................................................................................................... 80 7.7.5 MPU-401 Command Controller ..............................................................................................................81 7.7.6 MIDI UART .............................................................................................................................................82 7.7.7 MPU-401 Configuration Registers ..........................................................................................................82 7.7.7.1 Activate and I/O Base address......................................................................................................................... 83
7.8
PARALLEL PORT .......................................................................................................................... 83
IBM XT/AT Compatible, Bi-Directional and EPP Modes .........................................................................84 Extended Capabilities Parallel Port.........................................................................................................88
7.8.1 7.8.2
7.9 POWER MANAGEMENT ............................................................................................................... 98 7.10 SERIAL IRQ .............................................................................................................................. 102 7.11 8042 KEYBOARD CONTROLLER DESCRIPTION .............................................................................. 105
7.11.1 7.11.2 7.11.3 7.11.4 7.11.5 7.11.6 7.11.6.1 7.11.6.2 7.11.7 7.11.8 7.11.9 Keyboard Interface............................................................................................................................106 External Keyboard and Mouse Interface ...........................................................................................107 Keyboard Power Management..........................................................................................................107 Interrupts ...........................................................................................................................................108 Memory Configurations .....................................................................................................................108 Register Definitions ...........................................................................................................................108 Host I/F Data Register................................................................................................................................... 108 Host I/F Status Register................................................................................................................................. 108 External Clock Signal ........................................................................................................................108 Default Reset Conditions ..................................................................................................................109 Keyboard and Mouse PME Generation.............................................................................................112 GPIO Pins .........................................................................................................................................113 Description ........................................................................................................................................114 GPIO Control.....................................................................................................................................115 GPIO Operation ................................................................................................................................116 GPIO PME and SMI Functionality .....................................................................................................117 Either Edge Triggered Interrupts .......................................................................................................118 LED Functionality ..............................................................................................................................118
7.12
7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 7.12.6 7.12.7
GENERAL PURPOSE I/O......................................................................................................... 113
7.13
7.13.1
SYSTEM MANAGEMENT INTERRUPT (SMI) ......................................................................... 118
SMI Registers....................................................................................................................................119
7.14
7.14.1
PME SUPPORT ........................................................................................................................119
`Wake on Specific Key' Option ..........................................................................................................120
7.15
7.15.1 7.15.2
FAN SPEED CONTROL AND MONITORING .......................................................................... 121
Fan Speed Control ............................................................................................................................121 Fan Speed Monitoring.......................................................................................................................122
7.16
7.16.1 7.16.2
SECURITY FEATURE .............................................................................................................. 125
GPIO Device Disable Register Control .............................................................................................125 Device Disable Register ....................................................................................................................125
7.17
7.17.1 7.17.2
GAME PORT LOGIC ................................................................................................................ 125
Power Control Register .....................................................................................................................128 VREF Pin ..........................................................................................................................................128
7.18
HARDWARE MONITORING INTERFACE ........................................................................................... 129
7.18.1 Hardware Monitoring Interface Signal Definition ...............................................................................129 7.18.2 SMBus Interface................................................................................................................................129 7.18.2.1 SMBus Slave Interface.................................................................................................................................. 130 7.18.3 Hardware Monitoring Block ...............................................................................................................132 7.18.3.1 Input Monitoring ........................................................................................................................................... 132 7.18.3.2 Resetting the Hardware Monitoring Block.................................................................................................... 132 7.18.3.3 Reset Out Pin ................................................................................................................................................ 133 7.18.3.4 Monitoring Modes......................................................................................................................................... 133 7.18.3.5 Interrupt Status Registers .............................................................................................................................. 134 7.18.3.6 Low Power Modes ........................................................................................................................................ 134
SMSC DS - LPC47M192 Page 5 Rev. 03/30/05
DATASHEET
7.18.3.7 7.18.3.8 7.18.3.9 7.18.3.10 7.18.3.11 7.18.3.12
Analog Voltage Measurement....................................................................................................................... 135 Voltage ID..................................................................................................................................................... 135 Temperature Measurement............................................................................................................................ 135 Thermal / Voltage Interrupt Pin .................................................................................................................... 136 Input Safety................................................................................................................................................... 137 Layout Considerations .................................................................................................................................. 137
8 9
RUNTIME REGISTERS ..................................................................................................................... 139 CONFIGURATION ............................................................................................................................. 166 9.1 SYSTEM ELEMENTS ........................................................................................................................ 166
9.1.1 Primary Configuration Address Decoder ..............................................................................................166 9.1.1.1 Entering the Configuration State ................................................................................................................... 166 9.1.1.2 Exiting the Configuration State..................................................................................................................... 166
9.2
CONFIGURATION SEQUENCE ........................................................................................................... 167
9.2.1 Enter Configuration Mode.....................................................................................................................167 9.2.1.1 Configuration Mode ...................................................................................................................................... 167 9.2.2 Exit Configuration Mode .......................................................................................................................167 9.2.2.1 Programming Example.................................................................................................................................. 167
9.3 9.4 9.5 10 10.1 10.2 10.3 11
CHIP LEVEL (GLOBAL) CONTROL/CONFIGURATION REGISTERS [0X00-0X2F]..................................... 170 LOGICAL DEVICE CONFIGURATION/CONTROL REGISTERS [0X30-0XFF]............................................. 173 SMSC DEFINED LOGICAL DEVICE CONFIGURATION REGISTERS ....................................................... 178 REGISTERS FOR HARDWARE MONITORING BLOCK .............................................................. 184 REGISTER SUMMARY................................................................................................................... 184 INTERNAL ADDRESS REGISTER .................................................................................................... 184 VALUE OR LIMIT REGISTERS (15H-3DH) ....................................................................................... 184
Registers 3Eh-4Fh......................................................................................................................................... 186
10.3.1.1
OPERATIONAL DESCRIPTION..................................................................................................... 190 MAXIMUM GUARANTEED RATINGS................................................................................................ 190
Super I/O section (pins 1 to 100).......................................................................................................190 Hardware Monitoring Block (pins 101 to 128) ...................................................................................190 11.1.1 11.1.2
11.1 11.2
11.2.1 11.2.2 11.2.3 11.2.4
HARDWARE MONITORING BLOCK SPECIFICATIONS ........................................................................ 190
Key Specifications.............................................................................................................................190 Supply Current ..................................................................................................................................190 Operating Temperature.....................................................................................................................190 Operating Voltage Ratings ................................................................................................................190
11.3
11.3.1
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 191
Capacitance values for Pins..............................................................................................................196
12 13 14 15 16
TIMING DIAGRAMS ....................................................................................................................... 197 PACKAGE OUTLINE...................................................................................................................... 220 APPENDIX A - THERMAL DIODE PARAMETERS...................................................................... 221 APPENDIX B - ADC VOLTAGE CONVERSION........................................................................... 222 APPENDIX C - TEST MODE .......................................................................................................... 223 SUPER I/O BLOCK ....................................................................................................................... 223
Board Test Mode...............................................................................................................................223 16.1.1
16.1 16.2
16.2.1 16.2.2
HARDWARE MONITORING BLOCK ................................................................................................. 225
Board Test Mode...............................................................................................................................225 XNOR-Chain Test Mode ...................................................................................................................225
17 18
APPENDIX D - REFERENCE DOCUMENTS................................................................................. 227 LPC47M192 REVISIONS................................................................................................................ 228
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SMSC DS - LPC47M192
DATASHEET
TABLES Table 1 - Super I/O Block Addresses .........................................................................................................................27 Table 2 - Status, Data and Control Registers .............................................................................................................31 Table 3 - Internal 2 Drive Decode - Normal ...............................................................................................................34 Table 4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped....................................................................................35 Table 5 - Tape Select Bits ..........................................................................................................................................35 Table 6 - Drive Type ID ..............................................................................................................................................35 Table 7 - Precompensation Delays ...........................................................................................................................36 Table 8 - Data Rates ..................................................................................................................................................37 Table 9 - DRVDEN Mapping ......................................................................................................................................37 Table 10 - Default Precompensation Delays ..............................................................................................................37 Table 11 - FIFO Service Delay ..................................................................................................................................39 Table 12 - Status Register 0.......................................................................................................................................41 Table 13 - Status Register 1.......................................................................................................................................41 Table 14 - Status Register 2.......................................................................................................................................42 Table 15 - Status Register 3.......................................................................................................................................42 Table 16 - Description of Command Symbols ...........................................................................................................45 Table 17 - Instruction Set ...........................................................................................................................................48 Table 18 - Sector Sizes .............................................................................................................................................54 Table 19 - Effects of MT and N Bits...........................................................................................................................55 Table 20 - Skip Bit vs Read Data Command .............................................................................................................55 Table 21 - Skip Bit vs. Read Deleted Data Command...............................................................................................55 Table 22 - Result Phase Table ..................................................................................................................................56 Table 23 - Verify Command Result Phase Table ......................................................................................................57 Table 24 - Typical Values for Formatting...................................................................................................................58 Table 25 - Interrupt Identification...............................................................................................................................60 Table 26 - Drive Control Delays (ms) ........................................................................................................................61 Table 27 - Effects of WGATE and GAP Bits..............................................................................................................63 Table 28 - Addressing the Serial Port........................................................................................................................65 Table 29 - Interrupt Control Table .............................................................................................................................67 Table 30 - Baud Rates ................................................................................................................................................73 Table 31 - Reset Function Table ..................................................................................................................................73 Table 32 - Register Summary for an Individual UART Channel ..................................................................................74 Table 33 - MPU-401 HOST INTERFACE REGISTERS ............................................................................................79 Table 34 - MIDI Data Port ...........................................................................................................................................79 Table 35 - MPU-401 STATUS PORT..........................................................................................................................79 Table 36 - MIDI RECEIVE BUFFER EMPTY STATUS BIT.......................................................................................80 Table 37 - MIDI TRANSMIT BUSY STATUS BIT.........................................................................................................80 Table 38 - MPU-401 COMMAND PORT ......................................................................................................................80 Table 39 - Parallel Port Connector ...............................................................................................................................83 Table 40 - EPP Pin Descriptions .................................................................................................................................88 Table 41 - ECP Pin Descriptions ...............................................................................................................................90 Table 42 - ECP Register Definitions.............................................................................................................................90 Table 43 - Mode Descriptions ......................................................................................................................................91 Table 44a - Extended Control Register ........................................................................................................................94 Table 45 - Channel/Data Commands supported in ECP mode ....................................................................................96 Table 46 - PC/AT and PS/2 Available Registers ..........................................................................................................99 Table 47 - State of System Pins in Auto Powerdown .................................................................................................100 Table 48 - State of Floppy Disk Drive Interface Pins in Powerdown ..........................................................................100 Table 49 - I/O Address Map .......................................................................................................................................106 Table 50 - Host Interface Flags ...............................................................................................................................106 Table 51 - Status Register .........................................................................................................................................108 Table 52 - Resets.......................................................................................................................................................109 Table 53 - General Purpose I/O Port Assignments ....................................................................................................114 Table 54 - GPIO Configuration Summary ..................................................................................................................115 Table 55 - GPIO Read/Write Behavior ....................................................................................................................116 Table 56 - Different Modes for Fan ............................................................................................................................122 Table 57 - SMBus Write Byte Protocol.......................................................................................................................130 Table 58 - SMBus Read Byte Protocol.......................................................................................................................131 Table 59 - SMBus Send Byte Protocol.......................................................................................................................131 Table 60 - SMBus Receive Byte Protocol ..................................................................................................................131 Table 61 - Modified SMBus Receive Byte Protocol Response to ARA ......................................................................132 Table 62 - Runtime Register Block Summary ............................................................................................................139
SMSC DS - LPC47M192 Page 7 Rev. 03/30/05
DATASHEET
Table 63 - Runtime Register Block Description..........................................................................................................142 Table 64 - LPC47M192 Configuration Registers Summary.....................................................................................168 Table 65 - Chip Level Registers .................................................................................................................................170 Table 66 - Logical Device Registers...........................................................................................................................173 Table 67 - I/O Base Address Configuration Register Description............................................................................175 Table 68 - Interrupt Select Configuration Register Description ..................................................................................176 Table 69 - DMA Channel Select Configuration Register Description.......................................................................177 Table 70 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00]...............................................178 Table 71 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03]...............................................................179 Table 72 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] ..............................................................180 Table 73 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] ..............................................................181 Table 74 - KYBD, Logical Device 7 [Logical Device Number = 0x07] ........................................................................181 Table 75 - PME, Logical Device A [Logical Device Number = 0x0A] .........................................................................183 Table 76 - MPU-401 [Logical Device Number = 0x0B]...............................................................................................183 Table 77 - Thermal Diode Parameters ......................................................................................................................221 Table 78 - Analog-to-Digital Conversions for Hardware Monitoring Block.................................................................222
SMSC DS - LPC47M192
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FIGURES FIGURE 1 - LPC47M192 BLOCK DIAGRAM ............................................................................................................22 FIGURE 2 - MPU-401 MIDI INTERFACE ....................................................................................................................78 FIGURE 3 - MPU-401 INTERRUPT.............................................................................................................................81 FIGURE 4 - MIDI DATA BYTE EXAMPLE ...................................................................................................................82 FIGURE 5 - KEYBOARD LATCH...............................................................................................................................111 FIGURE 6 - MOUSE LATCH......................................................................................................................................111 FIGURE 7 - GPIO FUNCTION ILLUSTRATION ........................................................................................................116 FIGURE 8 - FAN TACHOMETER INPUT AND CLOCK SOURCE............................................................................123 FIGURE 9 - CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC .....................................................124 FIGURE 10 - SUGGESTED MINIMUM TRACK WIDTH AND SPACING..................................................................138 FIGURE 11 - USING A DIODE AS A REMOTE TEMPERATURE SENSING ELEMENT .........................................138 FIGURE 12 - POWER-UP TIMING ............................................................................................................................198 FIGURE 13 - INPUT CLOCK TIMING........................................................................................................................198 FIGURE 14 - PCI CLOCK TIMING.............................................................................................................................199 FIGURE 15 - RESET TIMING ....................................................................................................................................199 FIGURE 16 - OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS......................................................200 FIGURE 17 - INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS .......................................................200 FIGURE 18 - I/O WRITE ............................................................................................................................................200 FIGURE 19 - I/O READ..............................................................................................................................................201 FIGURE 20 - DMA REQUEST ASSERTION THROUGH LDRQ#..............................................................................201 FIGURE 21 - DMA WRITE (FIRST BYTE).................................................................................................................201 FIGURE 22 - DMA READ (FIRST BYTE) ..................................................................................................................201 FIGURE 23 - FLOPPY DISK DRIVE TIMING (AT MODE ONLY) ..............................................................................202 FIGURE 24 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE....................................................................................203 FIGURE 25 - EPP 1.9 DATA OR ADDRESS READ CYCLE .....................................................................................204 FIGURE 26 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE....................................................................................205 FIGURE 27 - EPP 1.7 DATA OR ADDRESS READ CYCLE .....................................................................................205 FIGURE 28 - PARALLEL PORT FIFO TIMING..........................................................................................................207 FIGURE 29 - ECP PARALLEL PORT FORWARD TIMING .......................................................................................208 FIGURE 30 - ECP PARALLEL PORT REVERSE TIMING ........................................................................................209 FIGURE 31 - IRDA RECEIVE TIMING.......................................................................................................................210 FIGURE 32 - IRDA TRANSMIT TIMING ....................................................................................................................211 FIGURE 33 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING..............................................................................212 FIGURE 34 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ...........................................................................213 FIGURE 35 - SETUP AND HOLD TIME ....................................................................................................................214 FIGURE 36 - SERIAL PORT DATA ...........................................................................................................................214 FIGURE 37 - JOYSTICK POSITION SIGNAL............................................................................................................215 FIGURE 38 - JOYSTICK BUTTON SIGNAL ..............................................................................................................215 FIGURE 39 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING........................................................................216 FIGURE 40 - MIDI DATA BYTE .................................................................................................................................217 FIGURE 41 - FAN OUTPUT TIMING .........................................................................................................................217 FIGURE 42 - FAN TACHOMETER INTPUT TIMING.................................................................................................217 FIGURE 43 - LED OUTPUT TIMING .........................................................................................................................218 FIGURE 44 - SMBUS TIMING ..................................................................................................................................219 FIGURE 45 - 128 PIN QFP PACKAGE OUTLINE, 14x20x2.7 BODY, 3.2 MM FOOTPRINT ..................................220 FIGURE 46 - XNOR-CHAIN TEST STRUCTURE......................................................................................................223
SMSC DS - LPC47M192
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2
PIN LAYOUT
HVSS HVSS HVSS HVSS D1D1+ HVCC HVCC +1.5V_IN +1.8V_IN VCCP_IN +2.5V_IN +3.3V_IN +5V_IN D0+ D0-/XNOR_IN HVSS HVCC 12V_IN/VID4 VID3 VID2 VID1 VID0 A0/RESET#/ THERM# SCLK SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GP40/DRVDEN0 GP41/DRVDEN1 nMTR0 nDSKCHG nDS0 CLKI32 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA GP42/nIO_PME VTR CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# LPCPD# GP43/DDRC PCI_CLK SER_IRQ VSS GP10 /J1B1 GP11 /J1B2 GP12 /J2B1 GP13 /J2B2 GP14 /J1X GP15 /J1Y GP16 /J2X
LPC47M192 128 PIN QFP
HVCC HVSS GP57/nDTR2 GP56/nCTS2 GP55/nRTS2 GP54/nDSR2 GP53/TXD2 (IRTX) GP52/RXD2 (IRRX) GP51/nDCD2 VCC GP50/nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC
SMSC DS - LPC47M192
GP17 /J2Y AVSS GP20/P17 GP21/P16/nDS1 GP22/P12/nMTR1 VREF GP24/SYSOPT GP25/MIDI_IN GP26/MIDI_OUT GP60/LED1 GP61/LED2 GP27/nIO_SMI GP30/FAN_TACH2 GP31/FAN_TACH1 VCC GP32/FAN2 GP33/FAN1 KDAT KCLK MDAT MCLK VSS IRRX2/GP34 IRTX2/GP35 GP36/nKBDRST GP37/A20M
Page 10
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Rev. 03/30/05
DATASHEET
3
PIN CONFIGURATION
NAME GP40/DRVDEN0 GP41/DRVDEN1 nMTR0 nDSKCHG nDS0 CLKI32 VSS nDIR nSTEP PIN # 33 34 35 36 37 38 39 40 41 NAME GP11 /J1B2 GP12 /J2B1 GP13 /J2B2 GP14 /J1X GP15 /J1Y GP16 /J2X GP17 /J2Y AVSS GP20/P17 PIN # 65 66 67 68 69 70 71 72 73 NAME VCC nINIT nSLCTIN PD0 PD1 PD2 PD3 PD4 PD5 PIN # 97 98 99 100 101 102 103 104 105 NAME GP54/nDSR2 GP55/nRTS2 GP56/nCTS2 GP57/nDTR2 HVSS HVCC SDA SCLK A0/RESET#/ THERM#/ XNOR_OUT VID0 VID1 VID2 VID3 12V_IN/VID4 HVCC HVSS D0-/XNOR_IN D0+ +5V_IN +3.3V_IN +2.5V_IN VCCP_IN +1.8V_IN +1.5V_IN HVCC HVCC D1+ D1HVSS HVSS HVSS HVSS
PIN # 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA GP42/nIO_PME VTR CLOCKI LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# PCI_RESET# LPCPD# GP43/DDRC PCI_CLK SER_IRQ VSS GP10 /J1B1
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GP21/P16/nDS1 GP22/P12/nMTR1 VREF GP24/SYSOPT GP25/MIDI_IN GP26/MIDI_OUT GP60/LED1 GP61/LED2 GP27/nIO_SMI GP30/FAN_TACH 2 GP31/FAN_TACH 1 VCC GP32/FAN2 GP33/FAN1 KDAT KCLK MDAT MCLK VSS IRRX2/GP34 IRTX2/GP35 GP36/nKBDRST GP37/A20M
74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
PD6 PD7 VSS SLCT PE BUSY nACK nERROR nALF nSTROBE RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 GP50/nRI2 VCC GP51/nDCD2 GP52/RXD2 (IRRX) GP53/TXD2 (IRTX)
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
SMSC DS - LPC47M192
Page 11
Rev. 03/30/05
DATASHEET
4
DESCRIPTION OF PIN FUNCTIONS
QFP PIN# NAME VCC VTR VREF VSS AVSS CLOCKI32 CLOCKI LAD[3:0] LFRAME# LDRQ# DESCRIPTION BUFFER NAME PWR WELL 1 2 1 NOTES
53, 65,93 18 44 7, 31, 60,76 40 6 19 23:20 24 25
26 27
PCI_RESET# LPCPD#
29 30
PCI_CLK SER_IRQ
51
GP30/ FAN_TACH2 GP31/ FAN_TACH1 GP32/ FAN2
POWER PINS (10) +3.3 Volt Supply Voltage +3.3 Volt Standby Supply Voltage Reference Voltage Ground Analog Ground CLOCKS (2) 32.768kHz Trickle Clock Input IS 14.318MHz Clock Input IS PROCESSOR/HOST LPC INTERFACE (10) Active high LPC I/O used for multiplexed PCI_IO command, address and data bus. Active low input indicates start of new cycle PCI_I and termination of broken cycle. Active low output used for encoded PCI_O DMA/Bus Master request for the LPC interface. Active low input used as LPC Interface PCI_I Reset. Active low input Power Down signal indicates PCI_I that the LPC47M192 should prepare for power to be shut-off on the LPC interface. PCI clock input. PCI_ICLK Serial IRQ pin used with the PCI_CLK pin PCI_IO to transfer LPC47M192 interrupts to the host. FAN CONTROL (4) General Purpose I/O. GPIO can be IO8 configured as an Open-Drain Output. /Fan Tachometer 2 Input General Purpose I/O. GPIO can be configured as an Open-Drain Output. /Fan Tachometer 1 Input General Purpose I/O /Fan Speed Control 2 Output Both functions can be configured as OpenDrain Output. General Purpose I/O /Fan Speed Control 1 Output Both functions can be configured as OpenDrain Output. FDD INTERFACE (14) Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. Write Gate Output. This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. Can be configured as an Open-Drain Output.
Page 12
VTR VCC VCC VCC VCC
3
VCC VCC 4
VCC VCC
VCC
5
52
IO8
VCC
5
54
IO12
VCC
5, 6
55
GP33/ FAN1
IO12
VCC
5, 6
16
nRDATA
IS
VCC
11
nWGATE
O12
VCC
SMSC DS - LPC47M192
Rev. 03/30/05
DATASHEET
QFP PIN# 10
NAME nWDATA
DESCRIPTION Write Disk Data Output. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. Can be configured as an Open-Drain Output. Head Select Output. This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. Can be configured as an Open-Drain Output. Step Direction Output. This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion. Can be configured as an Open-Drain Output. Step Pulse Output. This active low high current driver issues a low pulse for each track-to-track movement of the head. Can be configured as an Open-Drain Output. This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. The nDSKCHG bit also depends upon the state of the Force Disk Change bits in the Force Disk Change register (see Runtime Registers section). Drive Select 0 Output. Can be configured as an Open-Drain Output. Motor On 0 Output. Can be configured as an Open-Drain Output. This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. The nWRPRT bit also depends upon the state of the Force Write Protect bit in the FDD Option register (see the Configuration Registers section). This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. General Purpose I/O Drive Density Select 0 Output. Indicates the drive and media selected. Both functions can be configured as OpenDrain Output. General Purpose I/O Drive Density Select 1 Output. Indicates the drive and media selected. Both functions can be configured as OpenDrain Output.
Page 13
BUFFER NAME O12
PWR WELL VCC
NOTES
12
nHDSEL
O12
VCC
8
nDIR
O12
VCC
9
nSTEP
O12
VCC
4
nDSKCHG
IS
VCC
5 3 15
nDS0 nMTR0 nWRTPRT
O12 O12 IS
VCC VCC VCC
14
nTRK0
IS
VCC
13
nINDEX
IS
VCC
1
GP40/ DRVDEN0
IO12
VCC
2
GP41/ DRVDEN1
IO12
VCC
5
SMSC DS - LPC47M192
Rev. 03/30/05
DATASHEET
QFP PIN# 84 85 87
NAME RXD1 TXD1 nRTS1
DESCRIPTION SERIAL PORT 1 INTERFACE (8) Receiver serial data input for port 1. Transmit serial data output for port 1. Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. Active low Data Set Ready input for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR.
BUFFER NAME IS O12 O8
PWR WELL VCC VCC VCC
NOTES
88
nCTS1
I
VCC
89
nDTR1
O6
VCC
86
nDSR1
I
VCC
SMSC DS - LPC47M192
Page 14
Rev. 03/30/05
DATASHEET
QFP PIN# 91
NAME nDCD1
DESCRIPTION Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. INFRARED INTERFACE (2) Infrared Receive Input /General Purpose I/O. GPIO can be configured as an Open-Drain Output. Infrared Transmit Output /General Purpose I/O. GPIO can be configured as an Open-Drain Output. SERIAL PORT 2 INTERFACE (8) General Purpose I/O. GPIO can be configured as an Open-Drain Output. Receive Serial Data 2 Input. See RXD1 pin description above Infrared Receive Input General Purpose I/O. GPIO can be configured as an Open-Drain Output. Transmit Serial Data 2 Output. See TXD1 pin description above. Infrared Transmit Output General Purpose I/O. GPIO can be configured as an Open-Drain Output. Request to Send 2 Output. See nRTS1 pin description above. General Purpose I/O. GPIO can be configured as an Open-Drain Output. Clear to Send 2 Input. See nCTS1 pin description above. General Purpose I/O. GPIO can be configured as an Open-Drain Output. Data Terminal Ready Output. See nDTR1 pin description above.
Page 15
BUFFER NAME I
PWR WELL VCC
NOTES
90
nRI1
I
VCC
5
61
IRRX2/ GP34 IRTX2/ GP35
IS/O8
VCC
62
IO12
VTR
7, 8, 9
95
GP52/ RXD2 (IRRX) GP53/ TXD2 (IRTX) GP55/ nRTS2
IS/O8
VCC
5
96
IO12
VTR
5, 7, 8
98
IO8
VCC
5
99
GP56/ nCTS2
IO8
VCC
5
100
GP57/ nDTR2
IO8
VCC
5
SMSC DS - LPC47M192
Rev. 03/30/05
DATASHEET
QFP PIN# 97
NAME GP54/ nDSR2
DESCRIPTION General Purpose I/O. GPIO can be configured as an Open-Drain Output. Data Set Ready 2 Input. See nDSR1 pin description above. General Purpose I/O. GPIO can be configured as an Open-Drain Output. Data Carrier Detect 2 Input. See nDCD1 pin description above. General Purpose I/O. GPIO can be configured as an Open-Drain Output. Ring Indicator 2 Input. See nRI1 pin description above. PARALLEL PORT INTERFACE (17) This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be Configured as an Open-Drain Output. Port Data 0 I/O Port Data 1 I/O Port Data 2 I/O Port Data 3 I/O Port Data 4 I/O Port Data 5 I/O Port Data 6 I/O Port Data 7 I/O This high active input from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Another status input from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This is a status input from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. A low active input from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode.
Page 16
BUFFER NAME IO8
PWR WELL VCC
NOTES 5
94
GP51/ nDCD2
IO8
VCC
5
92
GP50/ nRI2
IO8
VCC
5
66
nINIT
OP14
VCC
67
nSLCTIN
OP14
VCC
68 69 70 71 72 73 74 75 77
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT
IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 IOP14 I
VCC VCC VCC VCC VCC VCC VCC VCC VCC
78
PE
I
VCC
79
BUSY
I
VCC
80
nACK
I
VCC
SMSC DS - LPC47M192
Rev. 03/30/05
DATASHEET
QFP PIN# 81
NAME nERROR
DESCRIPTION A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. This output goes low to cause the printer to automatically feed one line after each line is printed. The nALF output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. KEYBOARD/MOUSE INTERFACE (6) Keyboard Data I/O Keyboard Clock I/O Mouse Data I/O Mouse Clock I/O General Purpose I/O. GPIO can be configured as an Open-Drain Output. Keyboard Reset Open-Drain Output General Purpose I/O. GPIO can be configured as an Open-Drain Output. Gate A20 Open-Drain Output GAME PORT (8) General Purpose I/O. GPIO can be configured as an Open-Drain Output. Joystick 1 Button 1 Input General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 1 Button 2 Input General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 2 Button 1 Input General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 2 Button 2 Input General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 1 X-Axis I/O General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 1 Y-Axis I/O General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 2 X-Axis I/O
Page 17
BUFFER NAME I
PWR WELL VCC
NOTES
82
nALF
OP14
VCC
83
nSTROBE
OP14
VCC
56 57 58 59 63
KDAT KCLK MDAT MCLK GP36/ nKBDRST GP37/ A20M
IOD16 IOD16 IOD16 IOD16 IO8
VCC VCC VCC VCC VCC
5 5 10
64
IO8
VCC
10
32
GP10/ J1B1 GP11/ J1B2 GP12/ J2B1 GP13 J2B2 GP14/ J1X GP15/ J1Y GP16/ J2X
IS/O8
VCC
5
33
IS/O8
VCC
5
34
IS/O8
VCC
5
35
IS/O8
VCC
5
36
IO12
VCC
5
37
IO12
VCC
5
38
IO12
VCC
5
SMSC DS - LPC47M192
Rev. 03/30/05
DATASHEET
QFP PIN# 39
NAME GP17/ J2Y
DESCRIPTION General Purpose I/O. GPIO can be configured as an Open-Drain Output Joystick 2 Y-Axis I/O GENERAL PURPOSE I/O (11) General Purpose I/O. Power Management Event Output. This active low Power Management Event signal allows the LPC47M192 to request wakeup. Both functions can be configured as an Open-Drain Output. General Purpose I/O. GPIO can be configured as an Open-Drain Output. Device Disable Reg. Control Input General Purpose I/O 8042 P17 I/O Both functions can be configured as OpenDrain Output General Purpose I/O 8042 P16 I/O Drive Select 1 Output All three functions can be configured as Open-Drain Output. General Purpose I/O 8042 P12 I/O Motor on 1 Output All three functions can be configured as Open-Drain Output. General Purpose I/O. GPIO can be configured as an Open-Drain Output. System Option. At the trailing edge of PCI reset or VCC POR this pin is latched to determine the configuration base address: 0 = Index Base I/O Address 02E Hex; 1 = Index Base I/O Address 04E Hex. General Purpose I/O. GPIO can be configured as an Open-Drain Output. MPU-401 MIDI Input General Purpose I/O. GPIO can be configured as an Open-Drain Output. MPU-401 MIDI Output General Purpose I/O. GPIO can be configured as an Open-Drain Output. LED 1 Output General Purpose I/O. GPIO can be configured as an Open-Drain Output. LED 2 Output General Purpose I/O Active low System Management Interrupt Output Both functions can be configured as an Open-Drain Output.
BUFFER NAME IO12
PWR WELL VCC
NOTES 5
17
GP42/ nIO_PME
IO12
VTR
9
28
GP43/ DDRC GP20/ P17
IO8
VCC
5
41
IO8
VCC
5
42
GP21/ P16/ nDS1
IO12
VCC
5
43
GP22/ P12/ nMTR1
IO12
VCC
5
45
GP24 (SYSOPT)
IO8
VCC
5, 11
46
GP25/ MIDI_IN GP26/ MIDI_OUT GP60/ LED1 GP61 LED2 GP27/ nIO_SMI
IO8
VCC
5
47
IO12
VCC
5
48
IO12
VTR
5, 12,
49
IO12
VTR
5, 12,
50
IO12
VCC
5
SMSC DS - LPC47M192
Page 18
Rev. 03/30/05
DATASHEET
QFP PIN# 102, 111, 121, 122
NAME HVCC
DESCRIPTION HARDWARE MONITORING BLOCK (28) +3.3V VCC pin dedicated to the Hardware Monitoring block. Can be powered by +3.3V Standby power if monitoring in low power states is required. Analog Ground. Internally connected to all of the Hardware Monitoring Block circuitry. System Management Bus bi-directional Data. Open Drain output. System Management Bus Clock. The lowest order programmable bit of the SMBus Address Input. Minimum 20msec low Reset output pulse Interrupt output for temperature and voltage interrupts. XNOR-Chain test mode Output The RESET# and THERM# are Open-Drain Outputs Voltage ID 0 Input Voltage ID 1 Input Voltage ID 2 Input Voltage ID 3 Input Defaults to Analog Input for +12V. Optionally, can be configured to read the VID4 Digital Input, a voltage supply readout from the processor. This value is read in the VID4 Register. Analog input for +5V Analog input for +3.3V Analog input for +2.5V Analog input for +Vccp (processor voltage: 0 to 3.0V). Analog input for +1.8V Analog Input for +1.5V This is the negative Analog input (current sink) from the remote thermal diode. This serves as the negative input into the A/D. Digital Input. If held high at power-up, initiates XNOR chain test mode. This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. See D0+ description. See D0- negative analog input description.
BUFFER NAME
PWR WELL 1
NOTES
101, 112, 125, 126, 127, 128 103 104 105
HVSS
1
SDA SCLK A0/ RESET#/ THERM#/ XNOR_OUT
IMOD3 IM IMO3
HVCC HVCC HVCC
106 107 108 109 110
VID0 VID1 VID2 VID3 12V_IN/ VID4
IM IM IM IM IANG /IM
HVCC HVCC HVCC HVCC HVCC
115 116 117 118 119 120 113
+5V_IN +3.3V_IN +2.5V_IN Vccp_IN +1.8V_IN +1.5V_IN D0-/
IANG IANG IANG IANG IANG IANG IANG /IM
HVCC
XNOR_IN 114 D0+
IANG
HVCC
123 124 Note: Note 1: Note 2: Note 3:
D1+ D1-
IANG IANG
HVCC HVCC
The "n" as the first letter of a signal name or the "#" as the suffix of a signal name indicates an "Active Low" signal. VCC and VSS pins are for Super I/O Blocks. HVCC and HVSS are dedicated for the Hardware Monitoring Block. VTR can be connected to VCC if no wakeup functionality is required. If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and "wake on specific key" logic. Set this bit to `1' if the clock is not connected.
Page 19 Rev. 03/30/05
SMSC DS - LPC47M192
DATASHEET
The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal follows the protocol defined for the LRESET# signal in the "Low Pin Count Interface Specification". Note 5: These pins are inputs to VCC and VTR powered logic. Note 6: The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset. Note 7: The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR (VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block. Note 8: The VCC power-up default for this pin is Logic "0" if the IRTX function is programmed on the GPIO. Note 9: These pins are inputs to VCC powered logic. Note 10: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must ensure that these pins are high. See Section "Pins That Require External Pullup Resistor". Note 11: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E. Note 12: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power.
Note 4:
4.1
Buffer Name Descriptions
Note: The buffer type values are specified at VCC=3.3V I IM IANG IS IMOD3 IMO3 O6 O8 OD8 IO8 IS/O8 O12 OD12 IO12 OD14 OP14 IOP14 IOD16 PCI_IO PCI_O PCI_I PCI_ICLK Input TTL Compatible - Super I/O Block. Input - Hardware Monitoring Block. Analog Input, Hardware Monitoring Block. Input with Schmitt Trigger. Input/Output (Open Drain), 3mA sink. Input/Output, 3mA sink, 3mA source. Output, 6mA sink, 3mA source. Output, 8mA sink, 4mA source. Open Drain Output, 8mA sink. Input/Output, 8mA sink, 4mA source. Input with Schmitt Trigger/Output, 8mA sink, 4mA source. Output, 12mA sink, 6mA source. Open Drain Output, 12mA sink. Input/Output, 12mA sink, 6mA source. Open Drain Output, 14mA sink. Output, 14mA sink, 14mA source. Input/Output, 14mA sink, 14mA source. Backdrive protected. Input/Output (Open Drain), 16mA sink. Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2)
Note 1: See the "PCI Local Bus Specification," Revision 2.1, Section 4.2.2. Note 2: See the "PCI Local Bus Specification," Revision 2.1, Section 4.2.2 and 4.2.3.
4.2
Pins That Require External Pullup Resistors
4.2.1 SUPER I/O PINS
The following pins require external pullup resistors: KDAT KCLK MDAT MCLK GP36/KBDRST if KBDRST function is used GP37/A20M if A20M function is used GP20/P17 If P17 function is used as an Open Drain Output
SMSC DS - LPC47M192 Page 20 Rev. 03/30/05
DATASHEET
GP21/P16/nDS1 if P16 or nDS1 function is used as Open Drain Output GP22/P12/nMTR1 if P12 or nMTR1 function is used as Open Drain Output GP27/nIO_SMI if nIO_SMI function is used GP42/nIO_PME if nIO_PME function is used SER_IRQ GP40/DRVDEN0 if DRVDEN0 function is used as an Open Drain. GP41/DRVDEN1 if DRVDEN1 function is used as an Open Drain. nMTR0 if used as an Open Drain Output nDS0 if used as an Open Drain Output nDIR if used as an Open Drain Output nSTEP if used as an Open Drain Output nWDATA if used as an Open Drain Output nWGATE if used as an Open Drain Output nHDSEL if used as an Open Drain Output nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG GPIOs
4.2.2 HARDWARE MONITORING BLOCK PINS
The following pins require external pullup resistors to 3.3V only: SCLK SDA A0/RESET#/THERM#/XNOR_OUT if the RESET# or THERM# function is used. This limits the SMBus address to 0101101 (unless external circuitry is provided). See section 7.18.2 SMBus Interface. VID0-VID3 12V_IN/VID4 if VID4 function is used.
SMSC DS - LPC47M192
Page 21
Rev. 03/30/05
DATASHEET
5
BLOCK DIAGRAM
FAN_TACH1*
IRRX2*
IRTX2*
FAN1*
FAN_TACH2*
J1B1, J1B2*
J2B1, J2B2*
J1X, J1Y*
J2X, J2Y*
FAN2*
LED1* LEDs
CLK32 CLOCKI
CLOCK GEN
2nd Infrared Port
Game Port
Fan Control
LED2*
SER_IRQ PCI_CLK LAD[3:0] LFrame LDRQ PCI_RESET LPCPD IO_PME* IO_SMI* GP1[0:7]* GP2[0:2,4:7]* GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]* SDA SCL VID0 VID1 VID2 VID3 12V_IN/VID4 +5V_IN +3.3V_IN +2.5V_IN +1.8V_IN +1.5V_IN Vccp_IN HVCC HVSS A0/RESET#/THERM#/ XNOR_OUT
PD[7,0] SERIAL IRQ Internal Bus (Data, Address, and Control lines) Multi-Mode Parallel Port with ChiProtectTM / FDC MUX (see LPC47B27x) Busy, Slct, PE, ERROR, ACK STROBE, INIT, SLCTIN, ALF
LPC Bus Interface
TXD1, RXD1
Power Mgmt General Purpose I/O
LPC47M192 (128 QFP)
High-Speed 16550A UART PORT 1
CTS1, RTS1 DSR1, DTR1 DCD1, RI1 TXD2 (IRTX)*, RXD2 (IRRX)*
SMBus
High-Speed 16550A UART PORT 2
CTS2*, RTS2 * DSR2*, DTR2* DCD2*, RI2*
WDATA WCLOCK Hardware Monitoring SMC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION Keyboard/Mouse 8042 controller MIDI_IN* MPU-401 Serial Port MIDI_OUT*
KCLK, MCLK KDATA, MDATA GateA20* KRESET* P12*, P16*, P17*
RCLOCK RDATA
DIR, STEP, DSKCHG, DS0, DS1*
DRVDEN0*, DRVDEN1*
WGATE, HDSEL
MTR0, MTR1*,TRK0, INDEX, WRTPRT
RDATA, WDATA
Note 1: This diagram does not show power and ground connections. Note 2: Functions with "*" are located on multifunctional pins. This diagram is designed to show the various functions available on the chip (not pin layout).
D1+
D0+ D1-
D0-
FIGURE 1 - LPC47M192 BLOCK DIAGRAM
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6
POWER FUNCTIONALITY
The LPC47M192 has four power planes: VCC, HVCC, VREF, and VTR.
6.1
VCC/HVCC Power
The LPC47M192 is a 3.3 Volt part. The VCC/HVCC supply is 3.3 Volts (nominal). VCC is supply for Super I/O Block, and HVCC is supply for the Hardware Monitoring Block. See the "Operational Description" Section and the "Maximum Current Values" subsection.
6.1.1 3 VOLT OPERATION / 5 VOLT TOLERANCE
The LPC47M192 is a 3.3-Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V Max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC/HVCC powered circuitry). The 5V tolerant pins are applicable to the Super I/O Block only. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: LAD[3:0] LFRAME# LDRQ# LPCPD# The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins in the Super I/O Block: PCI_RESET# PCI_CLK SER_IRQ IO_PME# The Hardware Monitoring Block digital pins are 3.3V only.
6.2
VREF Pin
The LPC47M192 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply. It is used for the game port. See the "GAME PORT LOGIC" section.
6.3
VTR Support
The LPC47M192 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and Maximum Current Values subsection. If the LPC47M192 is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 s before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential difference between the two supplies must not exceed 500mV.
6.3.1 TRICKLE POWER FUNCTIONALITY
When the LPC47M192 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events: UART 1 Ring Indicator UART 2 Ring Indicator Keyboard data Mouse data "Wake on Specific Key" Logic
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Fan Tachometers (Note) GPIOs for wakeup. See below. Note: The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 see below): Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low following a VCC POR and PCI Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin which comes up as output and low following a VTR POR, a VCC POR and PCI Reset. GP43 reverts to the basic GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output buffer type is retained. The other GPIOs function as follows: GP34, GP36, GP37 and GP40: Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR, and are not used for wakeup. GP35, GP42, GP53, GP60 and GP61: Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are powered by VTR so that the pins are always forced low when not used. GP35 and GP53 cannot be used for wakeup. GP42 is the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR. The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are powered by VTR so that they are driven low when VCC = 0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block. The following list summarizes the blocks, registers and pins that are powered by VTR: PME interface block PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers) "Wake on Specific Key" logic LED control logic Fan Tachometers Pins for PME Wakeup: GP42/nIO_PME (output, buffer powered by VTR) nRI1 (input) GP50/nRI2 (input) KDAT (input) MDAT (input) GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61) - all input-only except GP53, GP60, GP61. See below.
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Other Pins: IRTX2/GP35 (output, buffer powered by VTR) GP53/TXD2(IRTX) (output, buffer powered by VTR) GP60/LED1 (output, buffer powered by VTR) GP61/LED2 (output, buffer powered by VTR)
6.4
32.768 kHz Trickle Clock Input
The LPC47M192 utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink and wake on specific key function.
6.4.1 INDICATION OF 32KHZ CLOCK
There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M192. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded). Bit 0 controls the source of the 32kHz (nominal) clock for the fan tachometer logic, the LED blink logic and the "wake on specific key" logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer, LED and "wake on specific key" logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the fan tachometer, LED and "wake on specific key" logic. The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. These functions will work under VCC power even if the external 32 kHz clock is not connected. Fan Tachometer Wake on specific key LED blink
6.5
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as Vcc cycles on and off. When the internal PWRGOOD signal is "1" (active), Vcc > 2.3V (nominal), and the LPC47M192 host interface is active. When the internal PWRGOOD signal is "0" (inactive), Vcc <= 2.3V (nominal), and the LPC47M192 host interface is inactive; that is, LPC bus reads and writes will not be decoded. The LPC47M192 device pins IO_PME#, CLOCKI32, KDAT, MDAT, nRI1, nRI2, RXD2 and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.
6.6
Maximum Current Values
See the "Operational Description" section for the maximum current values.
6.6.1 SUPER I/O FUNCTIONS
The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs transitioning from/to 0V to/from 3.3V. The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that is driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1, GP61/LED2, and CLKI32. These pins, if configured as pushpull outputs, will source a minimum of 6mA at 2.4V when driving. The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs transitioning from/to 0V to/from 3.3V.
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6.6.2 HARDWARE MONITORING BLOCK FUNCTIONS
The maximum supply current for the Hardware Monitoring block, powered by HVCC, is shown in "Hardware Monitoring Block Specifications" section of the "Operation Description" section.
6.7
Power Management Events (PME/SCI)
The LPC47M192 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the "PME Support" section.
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7
FUNCTIONAL DESCRIPTION
The following sections describe the functional blocks located in the LPC47M192 (see FIGURE 1). All the functional blocks are dedicated to the Super I/O portion of the chip, except for the Hardware Monitoring block. The Hardware Monitoring block is maintained separately from the Super I/O components and is defined in section 7.18 - Hardware Monitoring Interface. It is powered by HVCC and all its registers are accessed through an Internal Address register located in the Hardware Monitoring block (see section 10 - Registers for Hardware Monitoring Block). The various Super I/O components are described in the following sections and their registers are implemented as typical Plug-and-Play components (see section 9 - CONFIGURATION). It should be noted that there are two main interfaces used to access the components of this chip. The LPC interface is used to access the Super I/O registers and the SMBus is used to access the Hardware Monitoring registers.
7.1
Super I/O Registers
The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.
7.2
Host Processor Interface (LPC)
The host processor communicates with the LPC47M192 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Table 1 - Super I/O Block Addresses ADDRESS Base+(0-5) and +(7) Base+(0-7) Base1+(0-7) Base2+(0-7) BLOCK NAME Floppy Disk Serial Port Com 1 Serial Port Com 2 0 4 5 LOGICAL DEVICE NOTES
3 Parallel Port SPP Base+(0-3) EPP Base+(0-7) ECP Base+(0-3), +(400-402) ECP+EPP+SPP Base+(0-7), +(400-402) 60, 64 KYBD 7 Base + 0 Game Port 9 Base + (0-5F) Runtime Registers A Note 1 Base + (0-1) MPU-401 B Base + (0-1) Configuration Note: Refer to the configuration register descriptions for setting the base address. Note 1: Logical Device A is refered to as the Runtime Register block or PME Block and may be used interchangeably throughout this document.
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7.3
LPC Interface
The following sub-sections specify the implementation of the LPC bus.
7.3.1 LPC INTERFACE SIGNAL DEFINITION
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. SIGNAL NAME LAD[3:0] LFRAME# PCI_RESET# LDRQ# nIO_PME LPCPD# SER_IRQ PCI_CLK TYPE I/O Input Input Output OD Input I/O Input DESCRIPTION LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Encoded DMA/Bus Master request for the LPC interface. Power Mgt Event signal. Allows the LPC47M192 to request wakeup. Powerdown Signal. Indicates that the LPC47M192 should prepare for power to be shut on the LPC interface. Serial IRQ. PCI Clock.
Note: The CLKRUN# signal is not implemented in this part.
7.3.2 LPC CYCLES
The following cycle types are supported by the LPC protocol. CYCLE TYPE I/O Write I/O Read DMA Write DMA Read LPC47M192 ignores cycles that it does not support. 1 Byte 1 Byte 1 Byte 1 Byte TRANSFER SIZE
7.3.3 FIELD DEFINITIONS
The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M192. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.
7.3.4 LFRAME# USAGE
LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47M192 to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M192 monitors the bus to determine whether the cycle is intended for it. The use of LFRAME# allows the LPC47M192 to enter a lower power state internally. There is no need for the LPC47M192 to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. When the LPC47M192 samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
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7.3.5 I/O READ AND WRITE CYCLES
The LPC47M192 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times. Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. See the "Low Pin Count (LPC) Interface Specification" Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.
7.3.6 DMA READ AND WRITE CYCLES
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M192. DMA write cycles involve the transfer of data from the LPC47M192 to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M192 are 1, 2 or 4 bytes. See the "Low Pin Count (LPC) Interface Specification" Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.
7.3.7 DMA PROTOCOL
DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47M192 and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the "Low Pin Count (LPC) Interface Specification," Revision 1.0.
7.3.8 POWER MANAGEMENT
7.3.8.1 CLOCKRUN Protocol The CLKRUN# pin is not implemented in the LPC47M192. See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 8.1. LPCPD Protocol See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 8.2.
7.3.8.2
7.3.9 SYNC PROTOCOL
See the "Low Pin Count (LPC) Interface Specification" Revision 1.0, Section 4.2.1.8 for a table of valid SYNC values. 7.3.9.1 Typical Usage The SYNC pattern is used to add wait states. For read cycles, the LPC47M192 immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M192 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47M192 will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M192 uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M192 uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks.
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7.3.9.2
SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle. The LPC47M192 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.
7.3.9.3
SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M192 has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP.
7.3.9.4
SYNC Error Indication The LPC47M192 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M192, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M192. If the host was writing data to the LPC47M192, the data had already been transferred. In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.
7.3.9.5 7.3.9.6
I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy:
When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When PCI_RESET# goes active (low): the host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal. the LPC47M192 must ignore LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).
7.3.10 LPC TRANSFERS
7.3.10.1 7.3.10.1.1 Wait State Requirements I/O Transfers The LPC47M192 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). DMA Transfers The LPC47M192 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. See the example timing for the LPC cycles in the "Timing Diagrams" section.
7.3.10.1.2
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7.4
Floppy Disk Controller
The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. LPC47M192 supports two floppy drive directly (see "Direct Support for Two Floppy Drives" subsection). The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.
7.4.1 FDC INTERNAL REGISTERS
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDIN G 0 6 nDRV2 5 STEP 4 nTRK0 3 HDSEL 2 nINDX 1 nWP 0 DIR SECONDARY ADDRESS 370 371 372 373 374 374 375 376 377 377 R/W R R R/W R/W R W R/W R W REGISTER Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)
RESET COND.
1
0
N/A
0
N/A
N/A
0
BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.
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BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as "1". BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING RESET COND. 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1
BIT 0 DIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 HEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware reset or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 DRIVE SEL0 0 4 3 2 WDATA RDATA WGATE TOGGLE TOGGLE 0 0 0 1 MOT EN1 0 0 MOT EN0 0
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BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1
BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output.
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BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 nRESET 0 1 DRIVE SEL1 0 0 DRIVE SEL0 0
RESET COND.
BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. DRIVE 0 1 DOR VALUE 1CH 2DH
Table 3 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4
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Table 4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 nDS0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5
BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M192. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M192. TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 5 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 5 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3
Normal Floppy Mode Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are `0'. DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0
REG 3F3
Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0
Table 6 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit 0 0 0 0 1 1 0 1 1 Note: REGISTER 3F3 - DRIVE TYPE ID Bit 5 Bit 4 L0-CRF2 - B1 L0-CRF2 - B0 L0-CRF2 - B3 L0-CRF2 - B2 L0-CRF2 - B5 L0-CRF2 - B4 L0-CRF2 - B7 L0-CRF2 - B6
L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0
RESET COND.
This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. Table 7 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 PRECOMPENSATION DELAY (nsec) <2Mbps 0.00 41.67 83.34 125.00 166.67 208.33 250.00 Default 2Mbps 0 20.8 41.7 62.5 83.3 104.2 125 Default
Default: See Table 10
BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.
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Note:
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block Separator circuits will be turned off. The controller will come out of manual low power. Table 8 - Data Rates DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 DENSEL 1 1 0 0 1 1 0 0 1 1 0 0 DRATE(1) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins. Table 9 - DRVDEN Mapping DT1 0 DT0 0 DRVDEN1 (1) DRATE0 DRVDEN0 (1) DENSEL DRIVE TYPE 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) PS/2
1 0 1
0 1 1
DRATE0 DRATE0 DRATE1
DRATE1 nDENSEL DRATE0
Table 10 - Default Precompensation Delays DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps PRECOMPENSATION DELAYS 20.8 ns 41.67 ns 125 ns 125 ns 125 ns
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.
7 RQM
6 DIO
5 NON DMA
4 CMD BUSY
3
2
1 DRV1 BUSY
0 DRV0 BUSY
Reserved Reserved
BIT 0 - 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte. BIT 5 NON-DMA Reserved, read `0'. This part does not support non-DMA mode. BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required. BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 11 gives several examples of the delays with a FIFO. The data is based upon the following formula:
Threshold # x 1 DATA RATE x8 - 1.5 us = DELAY
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.
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Table 11 - FIFO Service Delay FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes MAXIMUM DELAY TO SERVICING AT 2 Mbps DATA RATE 1 x 4 us - 1.5 us = 2.5 us 2 x 4 us - 1.5 us = 6.5 us 8 x 4 us - 1.5 us = 30.5 us 15 x 4 us - 1.5 us = 58.5 us MAXIMUM DELAY TO SERVICING AT 1 Mbps DATA RATE 1 x 8 us - 1.5 us = 6.5 us 2 x 8 us - 1.5 us = 14.5 us 8 x 8 us - 1.5 us = 62.5 us 15 x 8 us - 1.5 us = 118.5 us MAXIMUM DELAY TO SERVICING AT 500 Kbps DATA RATE 1 x 16 us - 1.5 us = 14.5 us 2 x 16 us - 1.5 us = 30.5 us 8 x 16 us - 1.5 us = 126.5 us 15 x 16 us - 1.5 us = 238.5 us
DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes.
PC-AT Mode 7 DSK CHG N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 0 N/A 0 0 N/A
RESET COND.
BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 are read as `0'. BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E). PS/2 Mode 7 DSK CHG N/A 6 1 N/A 5 1 N/A 4 1 N/A 3 1 N/A 2 DRATE SEL1 N/A 1 DRATE SEL0 N/A 0 nHIGH DENS 1
RESET COND.
BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.
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BITS 1 - 2 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BITS 3 - 6 UNDEFINED Always read as a logic "1" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E). Model 30 Mode 7 DSK CHG RESET COND. N/A 6 0 0 5 0 0 4 0 0 3 2 1 DMAEN NOPREC DRATE SEL1 0 0 1 0 DRATE SEL0 0
BITS 0 - 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS 4 - 6 UNDEFINED Always read as a logic "0" BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E). CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 0 N/A 1 DRATE SEL1 1 0 DRATE SEL0 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT 2 - 7 RESERVED Should be set to a logical "0"
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PS/2 Model 30 Mode 7 0 RESET COND. N/A 6 0 N/A 5 0 N/A 4 0 N/A 3 0 N/A 2 1 NOPREC DRATE SEL1 N/A 1 0 DRATE SEL0 0
BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. BIT 3 - 7 RESERVED Should be set to a logical "0" Table 9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.
7.4.2 STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 12 - Status Register 0 BIT NO. 7,6 SYMBOL IC NAME DESCRIPTION Interrupt Code 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. Seek End The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: Equipment Check 1. Step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". Head Address The current head address. Drive Select The current selected drive. Table 13 - Status Register 1 BIT NO. 7 SYMBOL EN NAME DESCRIPTION End of The FDC tried to access a sector beyond the final sector Cylinder of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". Data Error The FDC detected a CRC error in either the ID field or the data field of a sector.
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5
SE
4
EC
3 2 1,0
H DS1,0
6 5
SMSC DS - LPC47M192
DE
DATASHEET
BIT NO. 4
SYMBOL OR
NAME Overrun/ Underrun
3 2
ND
No Data
1 0
NW MA
Not Writeable Missing Address Mark
DESCRIPTION Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.
Table 14 - Status Register 2 BIT NO. 7 6 SYMBOL CM DESCRIPTION Unused. This bit is always "0". Control Mark Any one of the following: Read Data command - the FDC encountered a deleted data address mark. Read Deleted Data command - the FDC encountered a data address mark. Data Error in The FDC detected a CRC error in the data field. Data Field Wrong The track address from the sector ID field is different Cylinder from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". Bad Cylinder The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. Missing Data The FDC cannot detect a data address mark or a Address Mark deleted data address mark. Table 15 - Status Register 3 BIT NO. 7 6 5 4 3 2 1,0 SYMBOL WP NAME Write Protected DESCRIPTION Unused. This bit is always "0". Indicates the status of the WRTPRT pin. NAME
5 4 3 2 1
DD WC
BC
0
MD
T0 HD DS1,0
Unused. This bit is always "1". Track 0 Indicates the status of the TRK0 pin. Unused. This bit is always "1". Head Address Indicates the status of the HDSEL pin. Drive Select Indicates the status of the DS1, DS0 pins.
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RESET There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. PCI_RESET# Pin (Hardware Reset) The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in LD0-CRF0[3,2]. PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal. PS/2 mode This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is active low. Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
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DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0-CRF0[1]). CONTROLLER PHASES For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. Command Phase After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Please refer to Table 16 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. Non-DMA Mode - Transfers from the FIFO to the Host This part does not support non-DMA mode. Non-DMA Mode - Transfers from the Host to the FIFO This part does not support non-DMA mode. DMA Mode - Transfers from the FIFO to the Host The FDC generates a DMA request cycle when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer. DMA Mode - Transfers from the Host to the FIFO. The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required.
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Data Transfer Termination The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and endof-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. Result Phase The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. Command Set/Descriptions Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 16 for explanations of the various symbols used. Table 17 lists the required parameters and the results associated with each command that the FDC is capable of performing.
Table 16 - Description of Command Symbols SYMBOL C D D0, D1 NAME Cylinder Address Data Pattern Drive Select 0-1 DESCRIPTION The currently selected address; 0 to 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle. DS1 DS0 DRIVE 0 0 Drive 0 0 1 Drive 1 By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek. The final sector number of the current track.
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DIR DS0, DS1
Direction Control Disk Drive Select
DTL
Special Sector Size
EC EFIFO EIS
Enable Count Enable FIFO Enable Implied Seek End of Track
EOT
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Table 16 - Description of Command Symbols SYMBOL GAP GPL H/HDS HLT NAME Gap Length Head Address Head Load Time DESCRIPTION Alters Gap 2 length when using Perpendicular Mode. The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128 Bytes 01 256 Bytes 02 512 Bytes 03 1024 Bytes ... ... 07 16K Bytes The desired cylinder number. Write `0'. This part does not support non-DMA mode. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH.
HUT
Head Unload Time
LOCK
MFM MT
MFM/FM Mode Selector Multi-Track Selector
N
Sector Size Code
NCN ND OW PCN POLL PRETRK
New Cylinder Number Non-DMA Mode Flag Overwrite Present Cylinder Number Polling Disable Precompensation Start Track Number Sector Address
R
The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written.
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Table 16 - Description of Command Symbols SYMBOL RCN SC DESCRIPTION Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set. Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands. Step Rate Interval The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual delays. Status 0 Registers within the FDC which store status information after a command has been executed. This status information is available to Status 1 the host during the result phase after command execution. Status 2 Status 3 Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular drives. NAME Relative Cylinder Number Number of Sectors Per Track
SK
SRT
ST0 ST1 ST2 ST3 WGATE
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7.4.3 INSTRUCTION SET
Table 17 - Instruction Set READ DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS SK 0 0 1 1 0 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
SMSC DS - LPC47M192
READ DELETED DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS SK 0 1 1 0 0 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N
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PHASE Command
R/W W W W W W W W W W
D7 MT 0
D6 MFM 0
Execution Result R R R R R R R
WRITE DATA DATA BUS D5 D4 D3 D2 D1 D0 REMARKS 0 0 0 1 0 1 Command Codes 0 0 0 HDS DS1 DS0 C Sector ID information prior to Command execution. H R N EOT GPL DTL Data transfer between the FDD and system. ST0 Status information after Command execution. ST1 ST2 C Sector ID information after Command execution. H R N WRITE DELETED DATA DATA BUS D5 D4 D3 D2 D1 0 0 1 0 0 0 0 0 HDS DS1 C
PHASE Command
R/W W W W
D7 MT 0
D6 MFM 0
D0 1 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
W W W W W W Execution Result R R R R
H R N EOT GPL DTL Data transfer between the FDD and system. Status information after Command execution.
ST0 ST1 ST2 C
Sector ID information after Command execution.
R R R
H R N
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PHASE Command
R/W W W W
D7 0 0
D6 MFM 0
D5 0 0
READ A TRACK DATA BUS D4 D3 D2 D1 0 0 0 1 0 0 HDS DS1 C
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
W W W W W W Execution
H R N EOT GPL DTL Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT. Status information after Command execution.
Result
R R R R
ST0 ST1 ST2 C
Sector ID information after Command execution.
R R R
H R N VERIFY DATA BUS D4 D3 D2 1 0 1 0 0 HDS C
PHASE Command
R/W W W W
D7 MT EC
D6 MFM 0
D5 SK 0
D1 1 DS1
D0 0 DS0
REMARKS Command Codes Sector ID information prior to Command execution.
W W W W W W Execution Result R R R R
H R N EOT GPL DTL/SC No data transfer takes place. Status information after Command execution.
ST0 ST1 ST2 C
Sector ID information after Command execution.
R R R
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H R N
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PHASE Command Result
R/W W R
D7 0 1
D6 0 0
D5 0 0
VERSION DATA BUS D4 D3 D2 1 0 0 1 0 0
D1 0 0
D0 0 0
REMARKS Command Code Enhanced Controller
PHASE Command
R/W W W W W W W W
D7 0 0
D6 MFM 0
FORMAT A TRACK DATA BUS D5 D4 D3 D2 D1 0 0 1 1 0 0 0 0 HDS DS1 N SC GPL D C
D0 1 DS0
REMARKS Command Codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters
Execution for Each Sector Repeat:
W W W
H R N FDC formats an entire cylinder Status information after Command execution
Result
R R R R R R R
ST0 ST1 ST2 Undefined Undefined Undefined Undefined
PHASE Command Execution
R/W W W
D7 0 0
D6 0 0
D5 0 0
RECALIBRATE DATA BUS D4 D3 D2 D1 0 0 1 1 0 0 0 DS1
D0 1 DS0
REMARKS Command Codes Head retracted to Track 0 Interrupt.
PHASE Command Result
R/W W R R
D7 0
D6 0
SENSE INTERRUPT STATUS DATA BUS D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 ST0 PCN
REMARKS Command Codes Status information at the end of each seek operation.
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PHASE Command
R/W W W W
D7 0
SPECIFY DATA BUS D6 D5 D4 D3 D2 D1 0 0 0 0 0 1 SRT HUT HLT
D0 1 ND
REMARKS Command Codes
PHASE Command Result
R/W W W R
D7 0 0
D6 0 0
SENSE DRIVE STATUS DATA BUS D5 D4 D3 D2 D1 0 0 0 1 0 0 0 0 HDS DS1 ST3
D0 0 DS0
REMARKS Command Codes Status information about FDD
PHASE Command
R/W W W W
D7 0 0
D6 0 0
D5 0 0
SEEK DATA BUS D4 D3 D2 0 1 1 0 0 HDS NCN
D1 1 DS1
D0 1 DS0
REMARKS Command Codes
Execution
Head positioned over proper cylinder on diskette. CONFIGURE DATA BUS D4 D3 D2 1 0 0 0 0 POLL PRETRK
PHASE Command
R/W W W W W
D7 0 0 0
D6 0
D5 0
D1 1
D0 1 0
REMARKS Configure Information
0 0 EIS EFIFO
0 0 FIFOTHR
Execution
PHASE Command
R/W W W W
D7 1 0
D6 DIR 0
D5 0 0
RELATIVE SEEK DATA BUS D4 D3 D2 D1 0 1 1 1 0 0 HDS DS1 RCN DUMPREG DATA BUS D4 D3 D2 0 1 1
D0 1 DS0
REMARKS
PHASE Command
R/W W
D7 0
D6 0
D5 0
D1 1
D0 0
REMARKS *Note: Registers placed in FIFO
Execution Result
R R R R
PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3
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PHASE
R/W R R R R R R
D7
D6
D5 SRT
DUMPREG DATA BUS D4 D3 D2
D1 HUT
D0 ND
REMARKS
LOCK 0
HLT SC/EOT 0 D3 D2 D1 EIS EFIFO POLL PRETRK READ ID DATA BUS D4 D3 D2 0 1 0 0 0 HDS
D0
GAP WGATE FIFOTHR
PHASE Command Execution
R/W W W
D7 0 0
D6 MFM 0
D5 0 0
D1 1 DS1
D0 0 DS0
REMARKS Commands The first correct ID information on the Cylinder is stored in Data Register Status information after Command execution.
Result
R
ST0
Disk status after the Command has completed R R R R R R ST1 ST2 C H R N PERPENDICULAR MODE DATA BUS D5 D4 D3 D2 D1 0 1 0 0 1 D3 D2 D1 D0 GAP INVALID CODES DATA BUS D5 D4 D3 D2 D1 Invalid Codes ST0 LOCK DATA BUS D5 D4 D3 0 1 0 0 LOCK 0
PHASE Command
R/W W
D7 0 OW
D6 0 0
D0 REMARKS 0 Command Codes WGATE
PHASE Command Result
R/W W R
D7
D6
D0
REMARKS Invalid Command Codes (NoOp - FDC goes into Standby State) ST0 = 80H
PHASE Command Result
R/W W R
D7 LOCK 0
D6 0 0
D2 1 0
D1 0 0
D0 0 0
REMARKS Command Codes
SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins. responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). It is the user's
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7.4.4 DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed. Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO. After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command. N determines the number of bytes per sector (see Table 18 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred. Table 18 - Sector Sizes N 00 01 02 03 .. 07 SECTOR SIZE 128 bytes 256 bytes 512 bytes 1024 bytes ... 16 Kbytes
The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1. If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 19. At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command. After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 20 describes the effect of the SK bit on the Read Data command
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execution and results. Except where noted in Table 20, the C or R value of the sector address is automatically incremented (see Table 22). Table 19 - Effects of MT and N Bits MT 0 1 0 1 0 1 N 1 1 2 2 3 3 MAXIMUM TRANSFER CAPACITY 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 FINAL SECTOR READ FROM DISK 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
Table 20 - Skip Bit vs Read Data Command DATA ADDRESS MARK TYPE ENCOUNTERED Normal Data Deleted Data RESULTS CM BIT OF DESCRIPTION ST2 SET? OF RESULTS No Normal termination. Yes Address not incremented. Next sector not searched for. No Normal termination. Yes Normal termination. Sector not read ("skipped").
SK BIT VALUE 0 0
SECTOR READ? Yes Yes
1 1
Normal Data Deleted Data
Yes No
Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 21 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 21, the C or R value of the sector address is automatically incremented (see Table 22). Table 21 - Skip Bit vs. Read Deleted Data Command SK BIT VALUE 0 DATA ADDRESS MARK TYPE ENCOUNTERED Normal Data RESULTS SECTOR READ? Yes CM BIT OF ST2 SET? Yes DESCRIPTION OF RESULTS Address not incremented. Next sector not searched for. Normal termination. Normal termination. Sector not read ("skipped"). Normal termination.
0 1
Deleted Data Normal Data
Yes No
No Yes
1
Deleted Data
Yes
No
Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data
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fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a "1" if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0". This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. Table 22 - Result Phase Table MT 0 HEAD 0 1 1 0 1 FINAL SECTOR TRANSFERRED TO HOST Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT Less than EOT Equal to EOT ID INFORMATION AT RESULT PHASE C H R N NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC C+1 NC 01 NC NC NC R+1 NC NC LSB 01 NC NC NC R+1 NC C+1 LSB 01 NC
NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented. Write Data After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command. The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when N = 0 and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk.
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value. Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 22 and Table 23 for information concerning the values of MT and EC versus SC and EOT value. Definitions: # Sectors Per Side = Number of formatted sectors per each side of the disk. # Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1". Table 23 - Verify Command Result Phase Table SC/EOT VALUE TERMINATION RESULT SC = DTL Success Termination 0 0 EOT <= # Sectors Per Side Result Phase Valid SC = DTL Unsuccessful Termination 0 0 EOT > # Sectors Per Side Result Phase Invalid SC <= # Sectors Remaining AND Successful Termination 0 1 EOT <= # Sectors Per Side Result Phase Valid SC > # Sectors Remaining OR Unsuccessful Termination 0 1 EOT > # Sectors Per Side Result Phase Invalid SC = DTL Successful Termination 1 0 EOT <= # Sectors Per Side Result Phase Valid SC = DTL Unsuccessful Termination 1 0 EOT > # Sectors Per Side Result Phase Invalid SC <= # Sectors Remaining AND Successful Termination 1 1 EOT <= # Sectors Per Side Result Phase Valid SC > # Sectors Remaining OR Unsuccessful Termination 1 1 EOT > # Sectors Per Side Result Phase Invalid If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. MT EC
Note:
Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively). After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command.
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Table 24 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics. FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM 3x FC C2 GAP1 SYNC 50x 12x 4E 00 IDAM 3x FE A1 C Y L H D S N C GAP2 SYNC EOR 22x 12x C C 4E 00 DATA AM 3x FB A1 F8 C DATA R GAP3 GAP 4b C
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a 40x FF SYNC 6x 00 IAM FC GAP1 SYNC 26x 6x FF 00 IDAM FE C Y L H D S N C GAP2 SYNC EOR 11x 6x C C FF 00 DATA AM FB or F8 C DATA R GAP3 GAP 4b C
PERPENDICULAR FORMAT
GAP4a 80x 4E SYNC 12x 00 IAM 3x FC C2 GAP1 SYNC 50x 12x 4E 00 IDAM 3x FE A1 C Y L H D S N C GAP2 SYNC EOR 41x 12x C C 4E 00 DATA AM 3x FB A1 F8 C DATA R GAP3 GAP 4b C
Table 24 - Typical Values for Formatting SECTOR SIZE N SC GPL1 GPL2 07 09 128 00 12 00 10 10 19 128 512 02 08 18 30 46 87 FM 1024 03 04 2048 04 02 C8 FF 5.25" Drives FF 4096 05 01 C8 ... ... 0C 256 01 12 0A 20 32 256 01 10 512* 02 09 2A 50 F0 MFM 1024 03 04 80 2048 04 02 C8 FF FF 4096 05 01 C8 ... ... 128 0 0F 07 1B 3.5" Drives FM 256 1 09 0F 2A 512 2 05 1B 3A 256 1 0F 0E 36 MFM 512** 2 09 1B 54 1024 3 05 35 74 GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. FORMAT
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CONTROL COMMANDS Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost. Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 255 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 256 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller. Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference: PCN < NCN: PCN > NCN: Direction signal to drive set to "1" (step in) and issues step pulses. Direction signal to drive set to "0" (step out) and issues step pulses.
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command - Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.
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Sense Interrupt Status An interrupt signal is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command 2. End of Seek, Relative Seek, or Recalibrate command The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt. Table 25 - Interrupt Identification SE 0 1 1 IC 11 00 01 INTERRUPT DUE TO Polling Normal termination of Seek or Recalibrate command Abnormal termination of Seek or Recalibrate command
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command. Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 26. The values are the same for MFM and FM. DMA operation is selected by the ND bit. When ND is "0", the DMA mode is selected. This part does not support non-DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles.
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Configure The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements. Table 26 - Drive Control Delays (ms) 2M 64 4 .. 56 60 1M 128 8 .. 112 120 HUT 500K 300K 256 426 16 26.7 .. .. 224 373 240 400 250K 512 32 .. 448 480 2M 4 3.75 .. 0.5 0.25 HLT 00 01 02 .. 7F 7F Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1". POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired. FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte. Relative Seek The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit. DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. 2M 64 0.5 1 .. 63 63.5 1M 128 1 2 .. 126 127 500K 256 2 4 .. 252 254 300K 426 3.3 6.7 .. 420 423 250K 512 4 8 . 504 508 1M 8 7.5 .. 1 0.5 SRT 500K 300K 16 26.7 15 25 .. .. 2 3.33 1 1.67 250K 32 30 .. 4 2
0 1 .. E F
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DIR 0 1
ACTION Step Head Out Step Head In
The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0. As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 255 due to its limitation of issuing a maximum of 256 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area. To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary. A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 27 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent. The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the preerase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format. On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation.
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0). It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged. The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. The write pre-compensation given to a perpendicular mode drive will be 0ns. 3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-D3 are ignored. Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND: 1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value. 2. "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e all conventional mode. Table 27 - Effects of WGATE and GAP Bits LENGTH OF GAP2 FORMAT FIELD 22 Bytes 22 Bytes 22 Bytes 41 Bytes PORTION OF GAP 2 WRITTEN BY WRITE DATA OPERATION 0 Bytes 19 Bytes 0 Bytes 38 Bytes
WGATE 0 0 1 1
GAP 0 1 0 1
MODE Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps)
LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used. The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the PCI_RESET# pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.
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ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands. COMPATIBILITY The LPC47M192 was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.
7.4.5 DIRECT SUPPORT FOR TWO FLOPPY DRIVES
The MTR1# function is on pin 43. MTR1# is the second alternate function on the GP22 pin. Pin 43 has the IO12 buffer type. The MTR1# function is selectable as open drain or push pull as MTR0# is through bit 6 of the FDD Mode Register in CRF0 of LD 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode Register. The DS1# function is on pin 41. DS1# is the second alternate function on the GP21 pin. Pin 42 has IO12 buffer type. The DS1# function is selectable as open drain or push pull as DS0# is through bit 6 of the FDD Mode Register in CRF0 of Logical Device 0. This overrides the selection of the output type through bit 7 of the GPIO control register. It is also controlled by bit 7 of the FDD Mode register. See the Runtime Registers section for register information. Disk Change Support for Second Floppy Bit[1] in the Force Disk Change register supports the second floppy. Setting either of the Force Disk Change bits active forces the internal FDD nDSKCHG active when the appropriate drive has been selected. The Force Disk Change register is defined in the Runtime Registers section. Force Write Protect Support for Second Floppy Bit[0] in the Device Disable register and FDD Option register support floppy write protect. See the Runtime Registers section for Device Disable register description and the Configuration Registers section for FDD Option register description.
7.4.6 FDC SWAP BIT
The FDC_SWAP bit in the FDD Mode Register (configuration register 0xF0) can be used to swap Drive 0 and Drive 1. The FDC_SWAP is defined as follows: Bit[4] FDC_SWAP 0 = Do Not Swap (default) 1 = Swap Drive 0 (nDS, nMTR pins) with Drive 1 (nDS, nMTR pins)
7.5
SERIAL PORT (UART)
The LPC47M192 incorporates two full function UARTs. They are compatible with the 16450, the 16450 ACE registers and the 16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-toserial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.
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Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more information. REGISTER DESCRIPTION Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see "Configuration" section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The LPC47M192 contains two serial ports, each of which contain a register set as described below. Table 28 - Addressing the Serial Port DLAB* 0 0 0 X X X X X X X 1 1 A2 0 0 0 0 0 0 1 1 1 1 0 0 A1 0 0 0 1 1 1 0 0 1 1 0 0 A0 0 0 1 0 0 1 0 1 0 1 0 1 REGISTER NAME Receive Buffer (read) Transmit Buffer (write) Interrupt Enable (read/write) Interrupt Identification (read) FIFO Control (write) Line Control (read/write) Modem Control (read/write) Line Status (read/write) Modem Status (read/write) Scratchpad (read/write) Divisor LSB (read/write) Divisor MSB (read/write
*Note: DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible. TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete. INTERRUPT ENABLE REGISTER (IER) Address Offset = 1H, DLAB = 0, READ/WRITE The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M192. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1".
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Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source. Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These bits are always logic "0".
FIFO CONTROL REGISTER (FCR) Address Offset = 2H, DLAB = X, WRITE This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21). Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed. Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. Bit 4,5 Reserved Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt. INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty MODEM Status (lowest priority)
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Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below. Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending. Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table. Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending. Bits 4 and 5 These bits of the IIR are always logic "0". Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1. Bit 7 0 0 1 1 RCVR FIFO Bit 6 Trigger Level (BYTES) 0 1 1 4 0 8 1 14
Table 29 - Interrupt Control Table FIFO MODE ONLY BIT 3 0 0 INTERRUPT IDENTIFICATION REGISTER BIT 2 0 1 BIT 1 0 1 BIT 0 1 0 PRIORIT Y LEVEL Highest
0
1
0
0
Second
1
1
0
0
Second
INTERRUPT SET AND RESET FUNCTIONS INTERRUPT INTERRUPT INTERRUPT RESET TYPE SOURCE CONTROL None None Overrun Error, Reading the Line Receiver Line Parity Error, Status Register Status Framing Error or Break Interrupt Read Receiver Received Data Receiver Data Buffer or the FIFO Available Available drops below the trigger level. No Characters Have Been Removed From or Input to the Character Reading the RCVR FIFO Timeout Receiver Buffer during the last 4 Indication Register Char times and there is at least 1 char in it during this time
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FIFO MODE ONLY BIT 3
INTERRUPT IDENTIFICATION REGISTER BIT 2 BIT 1 BIT 0
0
0
1
0
0
0
0
0
INTERRUPT SET AND RESET FUNCTIONS INTERRUPT PRIORIT INTERRUPT INTERRUPT RESET Y LEVEL TYPE SOURCE CONTROL Reading the IIR Register (if Transmitter Transmitter Source of Holding Third Holding Register Interrupt) or Register Empty Writing the Empty Transmitter Holding Register Clear to Send or Data Set Ready Reading the MODEM MODEM Status Fourth or Ring Indicator Status or Data Carrier Register Detect
LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity
Stop
Serial Data This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows: The Start, Stop and Parity bits are not included in the word length. BIT 1 0 0 1 1 BIT 0 0 1 0 1 WORD LENGTH 5 Bits 6 Bits 7 Bits 8 Bits
Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information. BIT 2 0 1 1 1 1 WORD LENGTH -5 bits 6 bits 7 bits 8 bits NUMBER OF STOP BITS 1 1.5 2 2 2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed).
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Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. Bit 5 This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled. Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register. MODEM CONTROL REGISTER (MCR) Address Offset = 4H, DLAB = X, READ/WRITE This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1". Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled. Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur: 1. 2. 3. 4. 5. 6. 7. The TXD is set to the Marking State(logic "1"). The receiver Serial Input (RXD) is disconnected. The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD). The Modem Control output pins are forced inactive high. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also
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operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Bits 5 through 7 These bits are permanently set to logic zero. LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE Bit 0 Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO. Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this `start' bit twice and then takes in the `data'. Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time. Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit. Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty,
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Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.
MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read. Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1". Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated. Bit 4 This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR. Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR. Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.
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SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily. PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock. Table 30 shows the baud rates possible. Effect Of The Reset on Register File The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port. FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is cleared as soon as the FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the FIFO drops below the trigger level. C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO. It is reset when the FIFO is empty. When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows: A. A FIFO timeout interrupt occurs if all the following conditions exist: At least one character is in the FIFO. The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are programmed, the second one is included in this time delay). The most recent CPU read of the FIFO was longer than 4 continuous character times ago. This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the CPU reads the RCVR FIFO. When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read. B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
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Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode, the IIR is not affected since EIR bit 2=0. Bit 5 indicates when the XMIT FIFO is empty. Bit 6 indicates that both the XMIT FIFO and shift register are empty. Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. Table 30 - Baud Rates DESIRED BAUD RATE 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800 DIVISOR USED TO GENERATE 16X CLOCK 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 32770 32769 PERCENT ERROR DIFFERENCE 1 BETWEEN DESIRED AND ACTUAL 0.001 0.004 0.005 0.030 0.16 0.16 0.16 0.16 HIGH SPEED BIT2 X X X X X X X X X X X X X X X X X X X 1 1
1 Note : The percentage error for all baud rates, except where indicated otherwise, is 0.2%. Note 2: The High Speed bit is located in the Device Configuration Space.
Table 31 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg.
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REGISTER/SIGNAL TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO
RESET CONTROL RESET RESET/Read LSR RESET/Read RBR RESET/ReadIIR/Write THR RESET RESET RESET RESET RESET/ FCR1*FCR0/_FCR0 RESET/ FCR1*FCR0/_FCR0 High Low Low Low High High High High
RESET STATE
All Bits Low All Bits Low
Table 32 - Register Summary for an Individual UART Channel REGISTER ADDRESS* ADDR = 0 DLAB = 0 ADDR = 0 DLAB = 0 ADDR = 1 DLAB = 0 REGISTER SYMBOL BIT 0 BIT 1 RBR Data Bit 0 Data Bit 1 (Note 1) Transmitter Holding Register (Write THR Data Bit 0 Data Bit 1 Only) Interrupt Enable Register IER Enable Enable Received Transmitter Data Holding Available Register Interrupt Empty (ERDAI) Interrupt (ETHREI) Interrupt Ident. Register (Read Only) IIR "0" if Interrupt ID Interrupt Bit Pending FIFO Control Register (Write Only) FCR FIFO RCVR FIFO (Note 7) Enable Reset Line Control Register LCR Word Word Length Length Select Bit 0 Select Bit 1 (WLS0) (WLS1) REGISTER NAME Receive Buffer Register (Read Only) MODEM Control Register MCR Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (DCTS) Bit 0 Bit 0 Bit 8 Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (DDSR) Bit 1 Bit 1 Bit 9
ADDR = 2 ADDR = 2 ADDR = 3
ADDR = 4
ADDR = 5 ADDR = 6 ADDR = 7 ADDR = 0 DLAB = 1 ADDR = 1 DLAB = 1
Line Status Register MODEM Status Register Scratch Register (Note 4) Divisor Latch (LS) Divisor Latch (MS)
LSR MSR SCR DDL DLM
*DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
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Table 32 - Register Summary for an Individual UART Channel (continued) BIT 2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit XMIT FIFO Reset Number of Stop Bits (STB) OUT1 (Note 3) Parity Error (PE) Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10 BIT 3 Data Bit 3 Data Bit 3 Enable MODEM Status Interrupt (EMSI) Interrupt ID Bit (Note 5) DMA Mode Select (Note 6) Parity Enable (PEN) OUT2 (Note 3) Framing Error (FE) Delta Data Carrier Detect (DDCD) Bit 3 Bit 3 Bit 11 BIT 4 Data Bit 4 Data Bit 4 0 BIT 5 Data Bit 5 Data Bit 5 0 BIT 6 Data Bit 6 Data Bit 6 0 BIT 7 Data Bit 7 Data Bit 7 0
0 Reserved Even Parity Select (EPS) Loop Break Interrupt (BI) Clear to Send (CTS) Bit 4 Bit 4 Bit 12
0 Reserved Stick Parity 0 Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
FIFOs Enabled (Note 5) RCVR Trigger LSB Set Break 0 Transmitter Empty (TEMT) (Note 2) Ring Indicator (RI) Bit 6 Bit 6 Bit 14
FIFOs Enabled (Note 5) RCVR Trigger MSB Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO (Note 5) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR's are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
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NOTES ON SERIAL PORT OPERATION TXD2 PIN The inactive state of the TXD2 (pin 96) can be selected through the TXD2_MODE bit, bit 5 of the Serial Port 2 Mode configuration register (at 0xF0 in LD5). FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one character delay. Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs. One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt. The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).
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7.6
INFRARED INTERFACE
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX2 and IRRX2 pins. These can be selected through the configuration registers. IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform. The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform. If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This timeout starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. The following figure shows the block diagram of the IR components in the LPC47M192:
ACE Registers COM Host Interface ACE UART Sharp ASK IrDA SIR Output MUX IR COM
IR Options Register, Bit 6
IR Transmit Pins The following description pertains to the TXD2/IRTX and IRTX2 pins of the LPC47M192. Following a VTR POR, the IRTX and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met: IRTX2/GP35 Pin. This pin defaults to the IRTX2 function. 1. 2. This pin will remain low following a VCC POR until IRTX2 function is selected for the pin, serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the IR block (if IR is enabled through the IR Option Register for Serial Port 2). This pin will remain low following a VCC POR until the GPIO output function is selected for the pin, at which time the pin will reflect the state of the GPIO data bit if it is configured as an output.
GP53/TXD2(IRTX) Pin. This pin defaults to the GPIO output function. 1. This pin will remain low following a VCC POR until the TXD2 (IRTX) function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the IR transmit output of the IR block (if IR is enabled through the IR Option Register for Serial Port 2).
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2.
3.
This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of serial port 2. Following a VCC POR, setting the TXD2_MODE bit (bit 5 in Serial Port 2 Mode Register, 0xF0 in Logical Device 5 Configuration Registers) to `1' will change the state of the TXD2 pin from low to tristate, regardless of the function selected on the pin (GPIO of TXD2), regardless of the state of the activate bit for serial port 2 and regardless of the state of VCC. When VCC is removed from the part while the TXD2_MODE bit is set to `1', the TXD2 pin will remain tristate unless a VTR POR occurs, which will reset the TXD2_MODE bit. This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register bit 3) is set or the polarity bit in the GP53 control register is set.
When Serial Port 2 is subsequently deactivated, the TXD2/IRTX pin will be driven low. The TXD2_MODE bit is implemented for modems that do not assert the ring indicator pin when TXD2 is sensed low. If required, this bit should be used as follows: When the activate bit for serial port 2 is cleared prior to entering a sleep state, set the TXD2_MODE bit. When the activate bit for serial port 2 is set, upon exiting a sleep state clear the TXD2_MODE bit. The IRTX2 pin is not affected by the TXD2_MODE bit.
7.7
MPU-401 MIDI UART
7.7.1 OVERVIEW
Serial Port 3 is used exclusively in the LPC47M192 as an MPU-401-compatible MIDI Interface. The LPC47M192 MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a compatible UART (FIGURE 2). Each of these components are discussed in detail, below. Only the MPU-401 UART (pass-through) mode is included in this implementation. MPU-401 UART mode is supported on the Sound Blaster 16 Series-compatible MIDI hardware. The Sound Blaster 16 hardware is supported by Microsoft Windows Operating Systems. In MPU-401 UART mode, data is transferred without modification between the host and the MIDI device (UART). Once UART mode is entered using the UART MODE command (3Fh), the only MPU-401 command that the interface recognizes is RESET (FFh).
MPU-401 COMMAND CONTROLLER
SA[15:0] SD[7:0] nIOW nIOR IRQ HOST INTERFACE
UART
TX RX
MIDI_OUT MIDI_IN
CONFIGURATION REGISTERS
FIGURE 2 - MPU-401 MIDI INTERFACE Note: This figure is for illustration purposes only and is not intended to suggest specific implementation details.
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7.7.2 HOST INTERFACE
Overview The Host Interface includes two contiguous 8-bit run-time registers (the Status/Command Port and the Data Port), and an interrupt. For illustration purposes, the Host Interface block shown in FIGURE 2 uses standard ISA signaling. Address decoding and interrupt selection for the Host Interface are determined by device configuration registers (see Section "MPU-401Configuration Registers"). I/O Addresses The Sound Blaster 16 MPU-401 UART mode MIDI interface requires two consecutive I/O addresses with possible base I/O addresses of 300h and 330h. The default is 330h. The LPC47M192 MPU-401 I/O base address is programmable on even-byte boundaries throughout the entire I/O address range (see Section "Activate and I/O Base address"). Registers (Ports) The run-time registers in the MPU-401 Host Interface are shown below in Table 33. Table 33 - MPU-401 HOST INTERFACE REGISTERS REGISTER NAME MIDI DATA STATUS COMMAND ADDRESS MPU-401 I/O Base Address MPU-401 I/O Base Address + 1 MPU-401 I/O Base Address + 1 TYPE R/W R W DESCRIPTION Used for MIDI transmit data, MIDI receive data, and MPU-401 command acknowledge. Used to indicate the send/receive status of the MIDI Data port. Used for MPU-401 Commands.
7.7.3 MIDI DATA PORT
The MIDI Data port exchanges MIDI transmit and MIDI receive data between the MPU-401 UART interface and the host. The MIDI Data port is read/write (Table 34). The MIDI Data port is also used to return the command acknowledge byte `FEh' following host writes to the COMMAND port. The MIDI Data port is full-duplex; i.e., the transmit and receive buffers can be used simultaneously. An interrupt is generated when either MIDI receive data or a command acknowledge is available to the host in the MIDI Data register. See Section "Bit 7 - MIDI Receive Buffer Empty" and "Interrupt" Table 34 - MIDI Data Port MPU-401 I/O BASE ADDRESS D7 D6 D5 D4 D3 D2 R/W R/W R/W R/W R/W R/W MIDI DATA/COMMAND-ACKNOWLEDGE REGISTER D1 R/W D0 R/W DEFAULT n/a
TYPE NAME
7.7.4 STATUS PORT
The Status port is used to indicate the state of the transmit and receive buffers in the MIDI Data port. The Status port is read-only (Table 35). Status port Bit 6 is MIDI Transmit Busy, Bit 7 is MIDI Receive Buffer Empty. The remaining bits in the Status port are RESERVED. Table 35 - MPU-401 STATUS PORT MPU-401 I/O BASE ADDRESS+1 D7 D6 D5 D4 R R R R 0 MIDI RX MIDI TX 0 BUFFER BUSY EMPTY D3 R
0
TYPE BIT NAME
D2 R
0
D1 R
0
D0 R
0
DEFAULT 0x80
7.7.4.1 Bit 7 - MIDI Receive Buffer Empty Bit 7 MIDI Receive Buffer Empty indicates the read state of the MIDI Data port (Table 36). If the MRBE bit is `0', MIDI Read/Command Acknowledge data is available to the host. If the MRBE bit is `1', MIDI Read/Command Acknowledge data is NOT available to the host.
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The MPU-401 Interrupt output is active `1' when the MIDI Receive Buffer Empty bit is `0'. The MPU-401 Interrupt output is inactive `0' when the MIDI Receive Buffer Empty bit is `1'. See Section "Interrupt" for more information. Table 36 - MIDI RECEIVE BUFFER EMPTY STATUS BIT STATUS PORT D7 0 1 DESCRIPTION MIDI Read/Command Acknowledge data is available to the host. MIDI Read/Command Acknowledge data is NOT available to the host.
7.7.4.2 Bit 6 - MIDI Transmit Busy Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 37) There are no interrupts associated with MIDI transmit (write) data. Table 37 - MIDI TRANSMIT BUSY STATUS BIT STATUS PORT D6 0 1 DESCRIPTION The MPU-401 interface is ready to accept a data/command byte from the host. The MPU-401 interface is NOT ready to accept a data/command byte from the host.
Bits[5:0] RESERVED (Reserved bits cannot be written and return `0' when read). Command Port The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is writeonly (Table 38). See Section "MPU-401 Command controller" below. Table 38 - MPU-401 COMMAND PORT D7 W D6 W MPU-401 I/O BASE ADDRESS+1 D5 D4 D3 D2 W W W W COMMAND REGISTER D1 W D0 W DEFAULT n/a
TYPE NAME
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Interrupt The MPU-401 IRQ is asserted (`1') when either MIDI receive data or a command acknowledge byte is available tot he host in the MIDI data register (FIGURE 3). the IRQ is deasserted (`0') when the host reads the MIDI Data port. Note: If, following a host read, data is still available in the 16C550A Receive FIFO, the IRQ will remain asserted (`1'). The IRQ is enabled when the `Activate' bit in the MPU-401 configuration registers logical device block is asserted `1'. If the Activate bit is deasserted `0', the MPU-401 IRQ cannot be asserted (see Section "MPU-401 Configuration Registers"). The MPU-401 IRQ is not affected by MIDI write data, 16C550A transmit-related functions or Receiver Line Status interrupts. The factory default Sound Blaster 16 MPU-401 IRQ is 5.
NOTE: IRQ remains asserted until read FIFO is empty
MIDI_IN MIDI RX CLOCK DATA READY IRQ nREAD
4
MIDI RX DATA BYTE N
MIDI RX DATA BYTE N+1
1
3
2
FIGURE 3 - MPU-401 INTERRUPT NOTE1 DATA READY represents the Data Ready bit B0 in the 16C550A UART Line Status Register. NOTE2 nREAD represents host read operations from the MIDI Data register. NOTE3 IRQ is the MPU-401 Host Interface IRQ shown in FIGURE 2. The 16C550A UART Receive FIFO Threshold=1. NOTE4 MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32s.
7.7.5 MPU-401 COMMAND CONTROLLER
Overview Commands are written by the host to the MPU-401 MIDI Interface through the Command register (Table 33) and are immediately interpreted by the MPU-401 Command Controller shown in FIGURE 2. The MPU-401 Command Controller in this implementation only responds to the MPU-401 RESET (FFh) and UART MODE (3Fh) commands. All other commands are ignored. Under certain conditions, the Command Controller acknowledges MPU-401 commands with a command acknowledge byte (FEh). RESET Command The RESET command is FFh. The RESET command resets the MPU-401 MIDI Interface. Reset disables the MPU401 UART MODE command, disables the 16C550A UART, clears the receive FIFO. The command controller places the command acknowledge byte `FEh' in the MIDI Data port read buffer if the interface is not in the UART mode. The RESET command is executed but not acknowledged when the command is received while the interface is in the UART mode. When the MPU-401 is reset, receive data from the MIDI_IN port as well as data written by the host to the MIDI Data port is ignored. The MPU-401 MIDI Interface is reset following the RESET command or POR.
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UART MODE Command The UART MODE command is 3Fh. The UART MODE command clears the 16C550A transmit and receive FIFOs, places the command acknowledge byte (FEh) in the MIDI Data port receive buffer, and enables the 16C550A UART for transmit and receive operations. In UART mode, the MPU-401 Interface passes MIDI read and write data directly between the host (using the MIDI Data port) and the 16C550A UART Transmit and Receive buffers. The MPU-401 Command Controller ignores the UART MODE command when the MPU-401 Interface is already in UART mode. The MPU-401 RESET command is executed but not acknowledged by the MPU-401 Command Controller in UART MODE (see Section "RESET Command", above). Command Acknowledge Byte Under certain conditions, the command controller acknowledges the RESET and UART MODE commands with a command acknowledge byte (FEh). The command acknowledge byte appears as read-data in the MIDI Data port. Note: The command acknowledge byte will appear as the next available data byte in the receive buffer of the MIDI Data port. For example if the receive FIFO is not empty when an MPU-401 RESET command is received, the command acknowledge will appear first, before any unread FIFO data. In the examples above, the receive FIFO is cleared before the command acknowledge byte is placed in the MIDI Data port read buffer.
7.7.6 MIDI UART
Overview The UART is used to transmit and receive MIDI protocol data from the MIDI Data port in the Host Interface (see Section "Host Interface"). The MIDI protocol requires 31.25k Baud (1%) and 10 bits total per frame: 1 start bit, 8 data bits, no parity, and 1 stop bit. For example, there are 320 microseconds per serial MIDI data byte. MIDI data is transferred LSB first (Figure 7). The UART is configured in full-duplex mode for the MPU-401 MIDI Interface, with 16-byte send/receive FIFOs.
MIDI RX DATA BYTE (01H) MIDI RX CLOCK
1
MIDI_IN
FIGURE 4 - MIDI DATA BYTE EXAMPLE Note1 MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32s.
7.7.7 MPU-401 CONFIGURATION REGISTERS
The LPC47M192 configuration registers are in Logical Device B (see "Configuration" section). The configuration registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults for the Base Address and Interrupt Select configuration registers match the MPU-401 factory defaults.
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7.7.7.1 Activate and I/O Base address When the Activate bit D0 is `0', the MPU-401 I/O base address decoder is disabled, the IRQ is always deasserted, and the MPU-401 hardware is in a minimum power-consumption state. When the Activate bit is `1', the MPU-401 I/O base address decoder and the IRQ are enabled, and the MPU-401 hardware is fully powered. Register 0x60 is the MPU-401 I/O Base Address High Byte, register 0x61 is the MPU-401 I/O Base Address Low Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The valid MPU-401 I/O base address range is 0x0100 - 0x0FFE. See Section "Host Interface".
7.8
PARALLEL PORT
The LPC47M192 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bidirectional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below: DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT BASE ADDRESS + 00H BASE ADDRESS + 01H BASE ADDRESS + 02H BASE ADDRESS + 03H EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3 BASE ADDRESS + 04H BASE ADDRESS + 05H BASE ADDRESS + 06H BASE ADDRESS + 07H
The bit map of these registers is: D0 PD0 TMOUT D1 PD1 0 D2 PD2 0 nINIT PD2 PD2 PD2 PD2 PD2 D3 PD3 nERR SLC PD3 PD3 PD3 PD3 PD3 D4 PD4 SLCT IRQE PD4 PD4 PD4 PD4 PD4 D5 PD5 PE PCD PD5 PD5 PD5 PD5 PD5 D6 PD6 nACK 0 PD6 PD6 PD6 PD6 PD6 D7 PD7 nBUSY 0 PD7 PD7 PD7 PD7 PD7 Note 1 1 1 2 2 2 2 2
DATA PORT STATUS PORT CONTROL PORT EPP ADDR PORT EPP DATA PORT 0 EPP DATA PORT 1 EPP DATA PORT 2 EPP DATA PORT 3
STROBE AUTOFD PD0 PD0 PD0 PD0 PD0 PD1 PD1 PD1 PD1 PD1
Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Table 39 - Parallel Port Connector HOST CONNECTOR 1 2-9 10 11 PIN NUMBER 83 68-75 80 79 STANDARD nSTROBE PD<0:7> nACK BUSY EPP nWrite PData<0:7> Intr nWait nStrobe PData<0:7> nAck Busy, PeriphAck(3) ECP
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HOST CONNECTOR 12 13 14 15 16 17 (1) = Compatible Mode (3) = High Speed Mode
PIN NUMBER 78 77 82 81 66 67
STANDARD PE SLCT nALF nERROR nINIT nSLCTIN
EPP (User Defined) (User Defined) nDatastb (User Defined) nRESET nAddrstrb
ECP PError, nAckReverse (3) Select nAutoFd, HostAck(3) nFault (1) nPeriphRequest (3) nInit(1) nReverseRqst(3) nSelectIn(1,3)
Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.
7.8.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU. STATUS PORT ADDRESS OFFSET = 01H The Status Port is located at an offset of `01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows: BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is `0', writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is `1', the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register. BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected. BIT 4 SLT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected. BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper.
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BIT 6 nACK - ACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data. BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character. CONTROL PORT ADDRESS OFFSET = 02H The Control Port is located at an offset of `02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled. BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). Bits 6 and 7 during a read are a low level, and cannot be written.
EPP ADDRESS PORT ADDRESS OFFSET = 03H The EPP Address Port is located at an offset of `03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.
EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of `04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 SMSC DS - LPC47M192 Page 85 Rev. 03/30/05
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PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode. EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of `05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 2 ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of `06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of `07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.
EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated. EPP 1.9 Write The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances: 1. 2. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation 1. The host initiates an I/O write cycle to the selected EPP register. 2. If WAIT is not asserted, the chip must wait until WAIT is asserted. 3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid. 5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle.
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6.
7. 8.
a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances: 1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high. 2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive. Read Sequence of Operation 1. The host initiates an I/O read cycle to the selected EPP register. 2. If WAIT is not asserted, the chip must wait until WAIT is asserted. 3. The chip tri-states the PData bus and deasserts nWRITE. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 5. Peripheral drives PData bus valid. 6. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase. b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the LAD[3:0] signals, followed by the TAR to complete the read cycle. 8. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port. In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read. EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE. 2. The host initiates an I/O write cycle to the selected EPP register. 3. The chip places address or data on PData bus. 4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.
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5. 6. 7.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-out occurs. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data bus for the PData bus. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high. Read Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus. 2. The host initiates an I/O read cycle to the selected EPP register. 3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid. 4. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a time-out occurs. 5. The Peripheral drives PData bus valid. 6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. 9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. Table 40 - EPP Pin Descriptions EPP SIGNAL nWRITE PD<0:7> INTR nWAIT EPP NAME nWrite Address/Data Interrupt nWait TYPE O I/O I I EPP DESCRIPTION This signal is active low. It denotes a write operation. Bi-directional EPP byte wide address and data bus. This signal is active high and positive edge triggered. (Pass through with no inversion, Same as SPP). This signal is active low. It is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer. This signal is active low. It is used to denote data read or write operation. This signal is active low. When driven active, the EPP device is reset to its initial operational mode. This signal is active low. It is used to denote address read or write operation. Same as SPP mode. Same as SPP mode. Same as SPP mode.
nDATASTB nRESET nADDRSTB PE SLCT nERR
nData Strobe nReset Address Strobe Paper End Printer Selected Status Error
O O O I I I
Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required to be a low.
7.8.2 EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability.
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Vocabulary The following terms are used in this document: assert: forward: reverse: Pword: 1 0 When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. Host to Peripheral communication. Peripheral to Host communication A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits. A high level. A low level.
These terms may be considered synonymous: PeriphClk, nAck HostAck, nAutoFd PeriphAck, Busy nPeriphRequest, nFault nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is:
D7 data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr 0 compress 0 intrValue MODE 0 PD7 Addr/RLE nBusy 0 nAck 0 PError Direction D6 PD6 D5 PD5 D4 PD4 Select ackIntEn D3 PD3 nFault SelectIn D2 PD2 0 nInit D1 PD1 0 autofd D0 PD0 2 0 strobe 1 1 2 2 2 0 dmaEn 0 serviceIntr 0 Parallel Port DMA full empty 0 Note
Address or RLE field
Parallel Port Data FIFO ECP Data FIFO Test FIFO 1 Parallel Port IRQ nErrIntrEn
Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers. ECP IMPLEMENTATION STANDARD This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft. Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is
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to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. Table 41 - ECP Pin Descriptions NAME nStrobe PData 7:0 nAck PeriphAck (Busy) TYPE O I/O I I DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse. This signal deasserts to indicate that the peripheral can accept data. This signal handshakes with nStrobe in the forward direction. In the reverse direction this signal indicates whether the data lines contain ECP command information or data. The peripheral uses this signal to flow control in the forward direction. It is an "interlocked" handshake with nStrobe. PeriphAck also provides command information in the reverse direction. Used to acknowledge a change in the direction the transfer (asserted = forward). The peripheral drives this signal low to acknowledge nReverseRequest. It is an "interlocked" handshake with nReverseRequest. The host relies upon nAckReverse to determine when it is permitted to drive the data bus. Indicates printer on line. Requests a byte of data from the peripheral when asserted, handshaking with nAck in the reverse direction. In the forward direction this signal indicates whether the data lines contain ECP address or data. The host drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck also provides command information in the forward phase. Generates an error interrupt when asserted. This signal provides a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP Mode the peripheral is permitted (but not required) to drive this pin low to request a reverse transfer. The request is merely a "hint" to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. Always deasserted in ECP mode.
PError (nAckReverse)
I
Select nAutoFd (HostAck)
I O
nFault (nPeriphRequest)
I
nInit
O
nSelectIn
O
Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined. Table 42 - ECP Register Definitions NAME data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr
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ADDRESS (Note 1) +000h R/W +000h R/W +001h R/W +002h R/W +400h R/W +400h R/W +400h R/W +400h R +401h R/W +402h R/W
ECP MODES 000-001 011 All All 010 011 110 111 111 All
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Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. Table 43 - Mode Descriptions MODE 000 001 010 011 100 101 110 111 DESCRIPTION* SPP mode PS/2 Parallel Port mode Parallel Port Data FIFO mode ECP Parallel Port mode EPP mode (If this option is enabled in the configuration registers) Reserved Test mode Configuration mode
*Refer to ECR Register Description
DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of `00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU. Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of `01H' from the base address. Bits0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows: BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register. BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register. BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register. BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
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BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
DEVICE CONTROL REGISTER (dcr) ADDRESS OFFSET = 02H The Control Register is located at an offset of `02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed. BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction. ecpDFifo (ECP Data FIFO) ADDRESS OFFSET = 400H Mode = 011 Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
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tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines. The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics. The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits. The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached. Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written. cnfgA (Configuration Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 compress This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression. BIT 6 intrValue Returns the value of the interrupt to determine possible conflicts. BIT [5:3] Parallel Port IRQ (read-only) to Table 44B BITS [2:0] Parallel Port DMA (read-only) to Table 44C ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write and select the Mode.
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BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is 0). 0: Disables DMA unconditionally. BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt. case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached). case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data. Table 44a - Extended Control Register R/W 000: 001: 010: MODE Standard Parallel Port Mode . In this mode the FIFO is reset and common drain drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode. PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull). Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull). Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration register L3-CRF0. All drivers have active pull-ups (push-pull). Reserved Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the parallel port. All drivers have active pull-ups (push-pull). Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull).
011:
100: 101: 110: 111:
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Table 44B CONFIG REG B IRQ SELECTED BITS 5:3 15 14 11 10 9 7 5 All Others 110 101 100 011 010 001 111 000
DMA SELECTED 3 2 1 All Others
Table 44C CONFIG REG B BITS 2:0 011 010 001 000
OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010). Setting the mode to 011 or 010 will cause the hardware to initiate data transfer. If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001. Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above. ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it is necessary to initialize some of the port bits. The following are required: Set Set Set Set Direction = 0, enabling the drivers. strobe = 0, causing the nStrobe signal to default to the deasserted state. autoFd = 0, causing the nAutoFd signal to default to the deasserted state. mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively. Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction. The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty. ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the
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forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware. Table 45 - Channel/Data Commands supported in ECP mode Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) D7 D[6:0] 0 1 Run-Length Count (mode 0011 0X00 only) Channel Address (0-127) (0-127)
Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided. Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes. LPC Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupts generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.
An interrupt is generated when: 1) For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received. 2) For Programmed I/O:
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a) b)
When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO.
3) 4)
When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. When ackIntEn is 1 and the nAck signal transitions from a low to a high.
FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0. DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled. Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.
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Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same. Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. readIntrThreshold =(16-) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the FIFO in a single burst. Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes. writeIntrThreshold = (16-) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to . (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.
7.9
POWER MANAGEMENT
Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. FDC Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met: 1. 2. 3. 4. The motor enable pins of register 3F2H are inactive (zero). The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts). The head unload timer must have expired. The Auto powerdown timer (10msec) must have timed out.
An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met. Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown. Note: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands. DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective.
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Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part: 1. 2. 3. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part). A read from the MSR register. A read or write to the Data register.
Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. Register Behavior Table 46illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 46 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it. Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed. Pin Behavior The LPC47M192 is specifically designed for systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important. The pins of the LPC47M192 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part. Table 46 - PC/AT and PS/2 Available Registers AVAILABLE REGISTERS BASE + PC-AT PS/2 (MODEL 30) ACCESS PERMITTED ADDRESS Access to these registers DOES NOT wake up the part 00H ---SRA R 01H ---SRB R 02H DOR (1) DOR (1) R/W 03H ------04H DSR (1) DSR (1) W 06H ------07H DIR DIR R 07H CCR CCR W Access to these registers wakes up the part 04H MSR MSR R 05H Data Data R/W Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part. System Interface Pins Table 47 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged."
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Table 47 - State of System Pins in Auto Powerdown SYSTEM PINS LAD[3:0] LDRQ# LPCPD# LFRAME# PCI_RESET# PCI_CLK SER_IRQ STATE IN AUTO POWERDOWN Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged
FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 48 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 48 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA nWRTPRT nTRK0 nINDEX nDSKCHG nMTR0 nDS0 nDIR nSTEP nWDATA nWGATE nHDSEL DRVDEN[0:1] STATE IN AUTO POWERDOWN INPUT PINS Input Input Input Input Input OUTPUT PINS Tristated Tristated Active Active Tristated Tristated Active Active
UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. management operations: 1. 2. When set, these bits allow the following auto power
The transmitter enters auto powerdown when the transmit buffer and shift register are empty. The receiver enters powerdown when the following conditions are all met: A. B. Receive FIFO is empty The receiver is waiting for a start bit. While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes.
Note:
Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state. MPU-401 Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B6. When set, this bit allows the following auto power management operations 1. The transmitter enters auto powerdown when the transmit buffer and shift register are empty 2. The receiver enters powerdown when the following conditions are all met:
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A. B.
Receive FIFO is empty The receiver is waiting for a start bit.
Exit Auto Powerdown The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when MIDI_IN changes state. Parallel Port Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any of the following condition 1. EPP is not enabled in the configuration register 2. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any of the following condition 1. ECP is not enabled in the configuration register 2 SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.
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7.10 SERIAL IRQ
The LPC47M192 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams For SER_IRQ Cycle A) Start Frame timing with source sampled a low pulse on IRQ1
SL
or
START FRAME H R T
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME S R T S R T S R T
H PCI_CLK SER_IRQ Drive Source
IRQ1
START
1
Host Controller
None
IRQ1
None
Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. B) Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14 FRAME SRT PCI_CLK SER_IRQ Driver None
IRQ15 FRAME SRT
IOCHCK# FRAME SRT
STOP FRAME
NEXT CYCLE T
I
2
H
R
STOP1 IRQ15 None Host Controller
START 3
Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle Note 1: The next SER_IRQ cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stop Frame. Note 2: There may be none, one or more Idle states during the Stop Frame. Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time. Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The LPC47M192) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle
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2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame. An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle's mode. SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M192 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the LPC47M192 must drive the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ must be left tri-stated. During the Recovery phase the LPC47M192 must drive the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the LPC47M192 must tri-state the SER_IRQ. The LPC47M192 will drive the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame. The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data th Frame, (6 x 3) - 1 = 17 clock after the rising edge of the Start Pulse). SER_IRQ Sampling Periods SIGNAL SAMPLED Not Used IRQ1 nIO_SMI/IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15
SER_IRQ PERIOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
# OF CLOCKS PAST START 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47
The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt. The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the nIO_SMI pin via bit 7 of the SMI Enable Register 2.
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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame's low time is two clocks then the next SER_IRQ Cycle's sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. If the Stop Frame's low time is three clocks then the next SER_IRQ Cycle's sampled mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame's pulse. Latency Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. EOI/ISR Read Latency Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order. AC/DC Specification Issue All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state. Reset and Initialization The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system's IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller's responsibility to provide the default values to 8259's and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.
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7.11 8042 Keyboard Controller Description
The LPC47M192 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042 microcontroller CPU core. This section concentrates on the LPC47M192 enhancements to the 8042. For general information about the 8042, refer to the "Hardware Description of the 8042" in the 8-Bit Embedded Controller Handbook.
8042A
P27 P10 P26 TST0 P23 TST1 P22 P11
LS05 KDAT KCLK MCLK MDAT
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the LPC47M192.
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7.11.1 KEYBOARD INTERFACE
The LPC47M192 LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 49 shows how the interface decodes the control signals. In addition to the above signals, the host interface includes keyboard and mouse IRQs. Table 49 - I/O Address Map ADDRESS 0x60 0x64 Command Write Read Write Read BLOCK KDATA KDATA KDCTL KDCTL FUNCTION (NOTE 1) Keyboard Data Write (C/D=0) Keyboard Data Read Keyboard Command Write (C/D=1) Keyboard Status Read
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data Read. Keyboard Data Write This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This is an 8 bit read only register. If enabled by "ENABLE FLAGS", when read, the KIRQ output is cleared and the OBF flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software. Keyboard Command Write This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set. Keyboard Status Read This is an 8 bit read only register. Refer to the description of the Status Register for more information. CPU-to-Host Communication The LPC47M192 CPU can write to the Output Data register via register DBB. A write to this register automatically sets Bit 0 (OBF) in the Status register. See Table 50. Table 50 - Host Interface Flags 8042 INSTRUCTION OUT DBB FLAG Set OBF, and, if enabled, the KIRQ output signal goes high
Host-to-CPU Communication The host system can send both commands and data to the Input Data register. The CPU differentiates between commands and data by reading the value of Bit 3 of the Status register. When bit 3 is "1", the CPU interprets the register contents as a command. When bit 3 is "0", the CPU interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
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KIRQ If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the LPC47M192 CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes "DBB". (KIRQ is normally selected as IRQ1 for keyboard support.) If "EN FLAGS" has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low; a high forces KIRQ high. MIRQ If "EN FLAGS" has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to signify that the LPC47M192 CPU has read the DBB register. If "EN FLAGS" has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support). Gate A20 A general purpose P21 is used as a software controlled Gate A20 or user defined output. 8042 PINS The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec for all timing. A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. After 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains the output signal as 1. In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the pins cannot be programmed as input nor inverted through the GP configuration registers.
7.11.2 EXTERNAL KEYBOARD AND MOUSE INTERFACE
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the LPC47M192 provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. The LPC47M192 has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT, MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and output as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11. Note: External pull-ups may be required.
7.11.3 KEYBOARD POWER MANAGEMENT
The keyboard provides support for two power-saving modes: soft powerdown mode and hard powerdown mode. In soft powerdown mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power down mode the clock to the 8042 is stopped. Soft Power Down Mode This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution starts from program memory location 0. Hard Power Down Mode This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell. When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
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7.11.4 INTERRUPTS
The LPC47M192 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
7.11.5 MEMORY CONFIGURATIONS
The LPC47M192 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
7.11.6 REGISTER DEFINITIONS
7.11.6.1 Host I/F Data Register The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for more information. 7.11.6.2 Host I/F Status Register The Status register is 8 bits wide. Table 51 shows the contents of the Status register. Table 51 - Status Register D7 UD D6 UD D5 UD D4 UD D3 C/D D2 UD D1 IBF D0 OBF
Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the LPC47M192 CPU. UD C/D Writable by LPC47M192 CPU. These bits are user-definable. (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 = command). During a host data/command write operation, this bit is set to "1" if SA2 = 1 or reset to "0" if SA2 = 0. (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting this flag activates the LPC47M192 CPU's nIBF (MIRQ) interrupt if enabled. When the LPC47M192 CPU reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. (Output Buffer Full) - This flag is set to whenever the LPC47M192 CPU write to the output data register (DBB). When the host system reads the output data register, this bit is automatically reset.
IBF
OBF
7.11.7 EXTERNAL CLOCK SIGNAL
The LPC47M192 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
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7.11.8 DEFAULT RESET CONDITIONS
The LPC47M192 has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 52 for the effect of each type of reset on the internal registers. Table 52 - Resets DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg HARDWARE RESET (PCI_RESET#) Low Low Low Low N/A 00H
N/A: Not Applicable GATEA20 AND KEYBOARD RESET The LPC47M192 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. PORT 92 FAST GATEA20 AND KEYBOARD RESET Port 92 Register This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device 7, 0xF0) set to 1. This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions. Name Location Default Value Attribute Size Port 92 92h 24h Read/Write 8 bits
BIT 7:6 5 4 3 2 1 0
PORT 92 REGISTER FUNCTION Reserved. Returns 00 when read Reserved. Returns a 1 when read Reserved. Returns a 0 when read Reserved. Returns a 0 when read Reserved. Returns a 1 when read ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high. Alternate System Reset. This read/write bit provides an alternate system reset function. This function provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the nALT_RST signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. Before another nALT_RST pulse can be generated, this bit must be written back to a 0.
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nGATEA20 8042 P21 0 0 1 1 ALT_A20 0 1 0 1 System nA20M 0 1 1 1
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND'ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0). If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92 Register and this pulse is AND'ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
14us
~ ~ 8042
6us
P20 KRST
KBDRS P92 Bit 0 Pulse Gen
14us Note: When Port 92 is writes are ignored and return undefined
KRST_GA2 Bit 2 nALT RST
~ ~
6us
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible software. This signal is externally OR'ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard controller. Upon reset, this signal is driven low.
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Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below.
KLATCH Bit
VCC
D Q
KINT new
KINT
8042
CLR
RD 60
FIGURE 5 - KEYBOARD LATCH
MLATCH Bit
VCC
D Q
MINT new
MINT
8042
CLR
RD 60
FIGURE 6 - MOUSE LATCH
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The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: MLATCH - Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH - Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default), 1=KINT is the latched 8042 KINT. See the "Configuration" section for a description of this register.
7.11.9 KEYBOARD AND MOUSE PME GENERATION
The LPC47M192 sets the associated PME Status bits when the following conditions occur: Keyboard Interrupt Mouse Interrupt Active Edge on Keyboard Data Signal (KDAT) Active Edge on Mouse Data Signal (MDAT) These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic and refer to the "Runtime Registers" section for details on the PME Status and Enable registers. The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The keyboard data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is powered by VTR (VCC=0). When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042 can prevent the system from entering a sleep state or trigger false PME events. The LPC47M192 has "isolation" bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. These bits may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state. See the SMSC Application Note titled "Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts" for more information. The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7, Register 0xF0 (KRST_GA20) and are defined below. These bits reset on VTR POR only: Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to the mouse wakeup (PME) logic. 1=block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce undesired results. It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1, S2).
User Note Regarding External Keyboard and Mouse: This is an application matter resulting from the behavior of the external 8042 in the keyboard. When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven low. This sets the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the KDAT and MDAT signals cannot be isolated internal to the part. This causes an IO_PME# to be generated if the keyboard and/or mouse PME
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events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR. In this case, an IO_PME# will not be generated, since the keyboard and mouse PME enable bits are reset to zero on a VTR POR. The BIOS software needs to clear these PME status bits after power-up. Case 2: Keyboard and/or Mouse Powered by VCC The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC. In this case, an IO_PME# will be generated if the enable bits were set for wakeup, since the keyboard and mouse PME enable bits are VTR powered. Therefore, if the keyboard and mouse are powered by VCC, the enable bits for keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed (i.e., S3) to prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as PME and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after power-up.
7.12 GENERAL PURPOSE I/O
The LPC47M192 provides a set of flexible Input/Output control functions to the system designer through the 37 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME.
7.12.1 GPIO PINS
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the GPIO function except for GP34 and GP35 which default to IRRX2 and IRTX2.
GPIO PIN PIN# 32 33 34 35 36 37 38 39 41 42 43 45 46 47 50 51 52 54 55 61 62 63 64 1 2 17 PIN NAME (Default Func/ Alternate Funcs) GP10/J1B1 GP11/J1B2 GP12 /J2B1 GP13 /J2B2 GP14 /J1X GP15 /J1Y GP16 /J2X GP17 /J2Y GP20/P17 GP21/P16/nDS1 GP22/P12/nMTR1 GP24/SYSOPT GP25/MIDI_IN GP26/MIDI_OUT GP27/nIO_SMI GP30/FAN_TACH2 GP31/FAN_TACH1 GP32/FAN2 GP33/FAN1 IRRX2/GP34 IRTX2/GP35 GP36/nKBDRST GP37/A20M GP40/DRVDEN0 GP41/DRVDEN1 GP42/nIO_PME
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GPIO REGISTER PCI RESET Out - low Out - low Out - low VCC POR Out- low Out- low Out- low VTR POR In In In In In In In In In In In In In In In In In In In In Out low In In In In In REG OFFS ET (hex) 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D REG GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 GP20 GP21 GP22 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GP40 GP41 GP42 PCI RESET 0x00 0x00 0x04 VCC POR 0x00 0x00 0x04 VTR POR 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x05 0x04 0x01 0x01 0x01 0x01 0x01 SOFT RESET SMI/PME PME PME PME PME PME PME PME PME SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME nIO_SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME SMI SMI/PME SMI/nIO_PME
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PWR WELL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR VCC VCC VCC VCC VTR
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1, 2 1, 2
3, 4
1
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GPIO PIN PIN# 28 92 94 95 96 97 98 99 100 48 49 PIN NAME (Default Func/ Alternate Funcs) GP43/DDRC GP50/nRI2 GP51/nDCD2 GP52/RXD2(IRRX) GP53/TXD2 (IRTX) GP54/nDSR2 GP55/nRTS2 GP56/nCTS2 GP57/nDTR2 GP60/LED1 GP61/LED2 PWR WELL VCC VCC VCC VCC VTR VCC VCC VCC VCC VTR VTR PCI RESET In Out - low VCC POR In Out- low VTR POR In In In In Out- low In In In In In In REG OFFS ET (hex) 3E 3F 40 41 42 43 44 45 46 47 48 REG GP43 GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GP60 GP61
GPIO REGISTER PCI RESET Note 5 0x00 VCC POR Note 5 0x00 VTR POR 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x01 0x01 SOFT RESET SMI/PME SMI/PME PME PME PME PME SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME SMI/PME NOTES 1, 5 1 1 1 1, 3 1 1 1 1 1 1
Note 1: Note 2: Note 3:
Note 4: Note 5:
These pins are inputs to VCC and VTR powered logic. The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset. The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR (VCC=0V with VTR=3.3V). These pins will remain low following a VCC POR until IRTX function is selected by setting the activate bit, at which time the pin will reflect the state of the transmit output of the IR block. It will remain low following a VCC POR until GPIO input function is selected, at which time the pin will reflect the state of the GPIO data bit. The GP53/TXD2 (IRTX) pin will remain low following a VCC POR (in addition to conditions stated above) until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block. These pins are inputs to VCC powered logic. Bits [3:2] (Alternate Function Select bits) of this register are reset (cleared) on VCC POR and PCI Reset (and VTR POR).
7.12.2 DESCRIPTION
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the PME block see "Run Time Register" section. The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 53.
Table 53 - General Purpose I/O Port Assignments QFP PIN# DEFAULT FUNCTION ALT. FUNC. 1 ALT. FUNC. 2 ALT. FUNC. 3 DATA 1 REGISTER DATA REGISTER BIT NO. 0 1 2 3 4 5 6 7 0 1 2 3 4 REGISTER OFFSET (HEX) 4B
32 33 34 35 36 37 38 39 41 42 43 N/A 45 46 47
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Reserved GPIO (System Option) GPIO GPIO
Joystick 1 Button 1 Joystick 1 Button 2 Joystick 2 Button 1 Joystick 2 Button 2 Joystick 1 X-Axis Joystick 1 Y-Axis Joystick 2 X-Axis Joystick 2 Y-Axis P17 P16 P12
GP1
GP2 EETI EETI
4C
MIDI_IN MIDI_OUT
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QFP PIN#
DEFAULT FUNCTION
ALT. FUNC. 1
ALT. FUNC. 2
ALT. FUNC. 3
DATA 1 REGISTER
50 51 52 54 55 61 62 63 64 1 2 17 28 N/A 92 94 95 96 97 98 99 100 48 49 N/A
GPIO GPIO GPIO GPIO GPIO Infrared Rx Infrared Tx GPIO GPIO GPIO GPIO GPIO GPIO Reserved GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Reserved
SMI Output Fan Tachometer 2 Fan Tachometer 1 Fan Speed Control 2 Fan Speed Control 1 GPIO GPIO Keyboard Reset Gate A20 Drive Density Select 0 Drive Density Select 1 Power Management Event Device Disable Reg. Control Ring Indicator 2 Data Carrier Detect 2 Receive Serial Data 2 Transmit Serial Data 2 Data Set Ready 2 Request to Send 2 Clear to Send 2 Date Terminal Ready LED LED
GP3
GP4 EETI EETI GP5
DATA REGISTER BIT NO. 7 0 1 2 3 4 5 6 7 0 1 2
REGISTER OFFSET (HEX)
4D
4E
3 7:4 0 1 2 3 4 5 6 7 0 1 7:2 4F
EETI EETI
GP6
50
Note 1: The GPIO Data and Configuration Registers are located in PME block at the offset shown from PME_BLK address.
the
7.12.3 GPIO CONTROL
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the "Runtime Registers" section of this specification. Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] detemines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions and the nSMI Alternate functions. The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the GPIO function and when the pin is configured for the alternate function for all pins, with the exception of the DDRC function on GP43, the analog game port pins (J1X, J1Y, J2X, J2Y) and the either edge triggered interrupts. When the alternate function is selected for the analog joystick pins (GP14, GP15, GP16 and GP17), these pins become open drain, non-inverted outputs. The basic GPIO configuration options are summarized in Table 54.
Table 54 - GPIO Configuration Summary SELECTED FUNCTION DIRECTION BIT B0 0 0 1 1 POLARITY BIT B1 0 1 0 1
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DESCRIPTION
GPIO
Pin is a non-inverted output. Pin is an inverted output. Pin is a non-inverted input. Pin is an inverted input.
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7.12.4 GPIO OPERATION
GPIO Configuration Register bit-1 (Polarity)
GPIO Configuration Register bit-0 (Input/Output)
SD-bit GPx_nIOW
D-TYPE D Q
Transparent
0 1
Q
GPx_nIOR
D
GPIO PIN
GPIO Data Register Bit-n
FIGURE 7 - GPIO FUNCTION ILLUSTRATION
The operation of the GPIO ports is illustrated in FIGURE 7.
Note: FIGURE 7 is for illustration purposes only and is not intended to suggest specific implementation details. When the following functions are selected, the associated GPIO pins have bi-directional functionality:
P12, P16, P17 and game port x-axis and y-axis inputs (J1X, J1Y, J2X, J2Y). When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect (Table 55) When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the last value written to the data register (Table 55). When the GPIO is programmed as an output, the pin is excluded from the PME and SMI logic.
Table 55 - GPIO Read/Write Behavior HOST OPERATION READ WRITE GPIO INPUT PORT LATCHED VALUE OF GPIO PIN NO EFFECT GPIO OUTPUT PORT LAST WRITE TO GPIO DATA REGISTER BIT PLACED IN GPIO DATA REGISTER
The LPC47M192 provides 31 GPIOs that can directly generate a PME. See the table in the next section. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in the PME_STS 2 register. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN 2 register and the PME_EN bit in the PME_EN register is set, a PME will be generated. These registers are located in the PME_BLK of runtime registers which are located at the address contained in the configuration registers 0x60 and
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0x61 in Logical Device A. The PME status bits for the GPIOs are cleared on a write of `1'. In addition, the LPC47M192 provides 19 GPIOs that can directly generate an SMI. See the table in the next section.
7.12.5 GPIO PME AND SMI FUNCTIONALITY
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 GP20-GP22, GP24-GP27 GP30-GP33 GP41, GP43 GP50-GP57 GP60, GP61 The following PME status and enable registers for these GPIOs: PME_STS2 and PME_EN2 for GP10-GP17 PME_STS3 and PME_EN3 for GP20-GP22, GP24-GP27 PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60 and GP61 PME_STS5 and PME_EN5 for GP50-GP57 The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable registers. GP20-GP22, GP24-GP26 GP30-GP33 GP41, GP42, GP43 GP54-GP57 GP60, GP61 The following SMI status and enable registers for these GPIOs: SMI_STS3 and SMI_EN3 for GP20-GP22, GP24-GP26 and GP60 SMI_STS4 and SMI_EN4 for GP30-GP33, GP41, GP42, GP43 and GP61 SMI_STS5 and SMI_EN5 for GP54-GP57, FAN_TACH1 and FAN_TACH2. The following GPIOs have "either edge triggered interrupt" (EETI) input capability. These GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs have a status bit in the MSC_STS status register that is set on both edges. The corresponding bits in the PME and SMI status registers are also set on both edges. GP21, GP22 GP41, GP43 GP60, GP61 The following table summarizes the PME and SMI functionality for each GPIO. It also shows the Either Edge Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on the I/O pads.
GPIO GP10-GP17 GP20-GP22, GP24-GP26 GP27 GP30, GP31 GP32, GP33 GP34 GP35 GP36, GP37 GP40 GP41 GP42 GP43 GP50-GP52 GP53 GP54-GP57 GP60, GP61 PME Yes Yes Yes Yes Yes No No No No Yes nIO_PME Yes Yes Yes Yes Yes SMI No Yes nIO_SMI Yes Yes Yes No No No Yes Yes Yes No No Yes Yes EETI No GP21, GP22 No No No No No No No Yes No Yes No No No Yes Buffer Power VCC VCC VCC VCC VCC VCC VTR VCC VCC VCC VTR VCC VCC VTR VCC VTR Notes 4 4 4 4 5
1 2 2 4 4, 6 4 1, 5 4 3, 4
Note 1: GP35 and GP53 have the IRTX function and their output buffers are powered by VTR so that the pins are always forced low when not used.
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Note 2: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These pins are not used for wakeup. Note 3: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is powered by VTR. Note 4: These pins can be used for wakeup events to generate a PME while the part is under VTR power (VCC=0). Note 5: These pins cannot be used for wakeup events to generate a PME while the part is under VTR power (VCC=0). The GP32, GP33 and GP53 pins come up as output and low on a VCC POR and PCI reset. Note 6: GP43 defaults to the GPIO function on VCC POR and PCI Reset.
7.12.6 EITHER EDGE TRIGGERED INTERRUPTS
Six GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22). A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are cleared on a write of `1'. There are also status bits for the EETIs located in the MSC_STS register, which are also cleared on a write of `1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin. Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status bits are cleared on a write of `1'. See the "Runtime Registers" section for more information. The configuration register for the either edge triggered interrupt status bits is defined in the "Runtime Registers" section.
7.12.7 LED FUNCTIONALITY
The LPC47M192 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A. The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed. In order to control a LED while the part is under VTR power, the GPIO pin must be configured for the LED function and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to blink the LED under VTR power. The LED will not blink under VTR power (VCC removed) if the external 32kHz clock is not connected. The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from VTR even when VCC is present. The LED control registers are defined in the "Runtime Register" section.
7.13 SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47M192 implements a "group" nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan tachometer pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active high or active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 5. The nSMI output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be
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enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be enabled onto the nIO_PME pin. Bit[5] of the SMI Enable Register 2 is used to enable the SMI output onto the nIO_PME pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in PME_STS3. See PME section for more details. An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows: nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and IRQ_FINT) or (EN_MPU401 and IRQ_MPU401) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT) or ENP12 and IRQ_P12)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
7.13.1 SMI REGISTERS
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers 3-5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a write of `1'. The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the corresponding enable bit in order to generate an SMI. The SMI registers are accessed at an offset from PME_BLK (see "Runtime Registers" section for more information). The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these status bits are not cleared by a write of `1'. The SMI logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an SMI. See the "Runtime Registers" section for the definition of these registers.
7.14 PME SUPPORT
The LPC47M192 offers support for power management events (PMEs), also referred to as a System Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset via the assertion of the nIO_PME signal. In the LPC47M192, the nIO_PME is asserted by active transitions on the ring indicator inputs nRI1 and nRI2, valid NEC infrared remote control frames, active keyboard-data edges, active mouse-data edges, programmable edges on GPIO pins and fan tachometer event. The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active low via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output.
Note: If the nRI2 pin is used for wakeup, the inactive state of the TXD2 pin may need to be changed. See the IR Transmit Pin section.
The PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is located at the address programmed in configuration registers 0x60 and 0x61 in Logical Device A. The PME Enable bit, PME_EN, globally controls PME Wake-up events. When PME_EN is inactive, the nIO_PME signal can not be asserted. When PME_EN is asserted, any wake source whose individual PME Wake Enable register bit is asserted can cause nIO_PME to become asserted. The PME Status register indicates that an enabled wake source has occurred, and if the PME_EN bit is set, asserted the nIO_PME signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_Status will become asserted independent of the state of the global PME enable bit, PME_EN. The following pertains to the PME status bits for each event: The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit. The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bits are cleared on a write of `1'.
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For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polairty bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write of `1'. The PME Wake registers also include status and enable bits for the fan tachometer input. See the "Keyboard and Mouse PME Generation" section for information about using the keyboard and mouse signals to generate a PME. In the LPC47M192 the nIO_PME pin can be programmed to be an open drain, active low, driver. The LPC47M192 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low; i.e., the nIO_PME signal is capable of being driven high externally by another active device or pullup even when the LPC47M192 VCC is grounded, providing VTR power is active. The LPC47M192 nIO_PME driver sinks 6mA at .55V max (see section 4.2.1.1 DC Specifications, page 122, in the "PCI Local Bus Specification," revision 2.1). The PME registers are run-time registers as follows. These registers are located in system I/O space at an offset from PME_BLK, the address programmed in Logical Device A at registers 0x60 and 0x61. The following registers are for GPIO wakeup events: PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2) PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3) PME Wake Status 4 (PME_STS4), PME Wake Enable 4 (PME_EN4) PME Wake Status 5 (PME_STS5), PME Wake Enable 5 (PME_EN5) See PME register description in the "Runtime Registers" Section.
Enabling SMI Events onto the PME Pin There is a bit in the PME Status Register 3 to show the status of the internal "group" SMI signal in the PME logic (if bit 5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3 register. This bit is defined as follows: 0=The group SMI output is inactive. 1 = The group SMI output is active. Note:
Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of `1'.
There is a bit in the PME Enable Register 3 to enable the SMI onto the nIO_PME pin (if the nIO_PME function is selected for GP42). This bit, DEVINT_EN, is at bit 3 of the PME_EN3 register. This bit will enable the internal "group" SMI signal (if bit 5 of the SMI_EN2 register is set) into the PME logic through the DEVINT_STS bit as follows: If the DEVINT_EN bit is `1' and the DEVINT_STS bit is `1' then the nIO_PME pin will be active. This pin has its polarity controlled by the polarity bit in the GP42 register. This bit is defined as follows: 0 = Disable group SMI output from the nIO_PME pin. 1 = Enable group SMI output onto the nIO_PME pin. That is, if this bit is set and the DEVINT_STS bit is set then a nPME is generated. Note: Bit 5 of the SMI_EN2 register must also be set.
7.14.1 `WAKE ON SPECIFIC KEY' OPTION
The LPC47M192 has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located in the primary base I/O address in Logical Device A. This register is powered by VTR and reset on VTR POR. The PME status bit for this event is located in the PME_STS1 register at bit 5 and the PME enable bit for this event is located in the PME_EN1 register at bit 5. See the "Runtime Registers" section for a definition of these registers. Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level. The following table shows the functions of the bits.
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Bit 1 2 3 4 5 6 7 8 9 10 11
Function Start bit (always 0) Data bit 0 (least significant bit) Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 (most significant bit) Parity bit (odd parity) Stop Bit (always 1)
The timing for the keyboard clock and data signals are shown in the "Timing Diagrams" section. The process to find a match for the scan code stored in the Keyboard Scan Code register is as follows: Begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has been high for 115-145usec. The data at this first clock edge is the start bit. The first data bit follows the start bit (clock 2). Sample the data on each falling edge of the clock. Store the eight bits following the stop bit to compare with the scan code stored in the Keyboard Scan Code register. Sample the comparator within 100usec of the falling edge of clock 9 (for example, at clock 10). Sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1's (odd parity). Repeat until a match is found. If the 8 data bits match the scan code stored in the Keyboard Scan Code register and the parity is correct, then it is considered a match. When a match is found and if the stop bit is 1, set the event status bit (bit 5 of the PME_STS1 register) to `1' within 100usec of the falling edge of clock 10. The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by setting the SPEKEY_EN bit (see following sub-section). The state machine will reset if there is a period where the clock remains high for more than one keyboard clock period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a false PME. The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Logical Device A is used to control the "wake-onspecific feature. This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the logic. The logic will draw no power when disabled. The bit is defined as follows: 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off
Note: The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register at bit 5) when the logic for feature is turned on.
7.15 FAN SPEED CONTROL AND MONITORING
The LPC47M192 can control the speed of two separate fans as well as monitor them if they are equipped with fan tachometer outputs. The following sections will clarify how this chip controls the speed of a fan and its' monitoring capabilities.
7.15.1 FAN SPEED CONTROL
The fan speed control for the LPC47M192 is implemented as pulse width modulators with fan clock speed selection. There are two pins, FAN1 and FAN2 (pins 55 and 54 respectively), that can control the speed of two separate fans. These signals are controlled by the Runtime registers FANx and Fan Control that are described below (see also section 8 - RUNTIME REGISTERS).
Note: These fan control pins come up as outputs and are low following a VCC POR and PCI Reset. These pins may not be used for wakeup events under VTR power (VCC=0).
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Fan Speed Control Summary The following table illustrates the different modes for the fans. Table 56 - Different Modes for Fan FANx Clock Control Bit (Note 1) 0 0 0 0 0 0 0 0 0 1 FANx Clock Multiplier Bit (Note 2) X 0 0 0 0 1 1 1 1 X FANx Clock Source Select Bit (Note 3) X 0 0 1 1 0 0 1 1 X FANx Clock Select Bit (Note 4) Fout 6-Bit Duty Cycle Control bits[6:1] (DCC) 0 1-63 Duty Cycle (%)
X 0 1 0 1 0 1 0 1 X
0Hz - LOW 15.625kHz 23.438kHz 40Hz 60Hz 31.25kHz 46.876kHz 80Hz 120Hz 0Hz - HIGH
(DCC/64) x 100
-
-
Note 1: This is FANx Register Bit 0 Note 2: This is Fan Control Register Bit 2 or 3 Note 3: This is Fan Control Register Bit 0 or 1 Note 4: This is FANx Register Bit 7 FANx Registers The FAN1 and FAN2 Registers are located at 0x56 and 0x57 from base I/O in Logical Device A. The bits are defined below. See the register description in the "Runtime Registers" section. Fan x Clock Select Bit, D7 The Fan x Clock select bit in the FANx registers is used with the Fan x Clock Source Select and the Fan x Clock Multiplier bits in the Fan Control register to determine the fan speed FOUT. See Table 56 above. Duty Cycle Control for Fan x, Bits D6 - D1 The Duty Cycle Control (DCC) bits determine the fan duty cycle. The LPC47M192 has 1.56% duty cycle resolution. When DCC = "000000" (min. value), FOUT is always low. When DCC is "111111" (max. value), FOUT is almost always high; i.e., high for 63/64th and low for 1/64th of the FOUT period. Generally, the FOUT duty cycle (%) is (DCC/64) x 100. Fan x Clock Control, Bit D0 The Fan x Clock Control bit D0 is used to override the Duty Cycle Control for Fan x bits and force FOUT always high. When D0 = "0", the DCC bits determine the FOUT duty cycle. When D0 = 1, FOUT is always high, regardless of the state of the DCC bits. Fan Control Register The Fan Control Register is located at 0x58 from base I/O in Logical Device A. The bits are defined below. See the register description in the "Runtime Registers" section. Fan x Count Divisor, Bits D7-D6 / D5-D4 Fan x Count Divisor bit in Fan Control Register is used to determine fan tachometer count. The choices for the divisor are 1, 2, 4 and 8. See "Fan Tachometer Input" section. Fan x Clock Multiplier, Bits D3 / D2 The Fan x Clock Multiplier bit is used with the Fan x Clock Source Select bit in the Fan Control Register and the Fan x Clock Select bit in Fan register to determine the FOUT. When the Fan x Clock Multiplier bit = "0", no clock multiplier is used. When the Fan x Clock Multiplier bit = "1", the clock speed determined by the Fan x Clock Source Select bit is doubled. Fan x Clock Source Select, Bits D1 / D0 The Fan x Clock Source Select and the Fan x Clock Multiplier bits in the Fan Control register is used with the Fan x Clock Select bit in the Fan x registers to determine the fan speed FOUT. See Table 56 above.
7.15.2 FAN SPEED MONITORING
The LPC47M192 monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. There are two pins that can be configured as the fan tachometer inputs (pins 51 and 52) which
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are monitored by using the Fan Tachometer registers. These signals, as well as the Fan Tachometer registers, are described below (see also section 8 - RUNTIME REGISTERS).
Fan Tachometer Inputs A fan tachometer input is used to measure the speed at which a fan is rotating. The fan tachometer input is a train of square pulses with a 50% duty cycle (see FIGURE 8) that are derived from the magnetic fields generated by the rotating rotor of the fan. The speed of the fan can be determined by calculating the period of the Fan Tachometer input pulse. Note: All calculations are based on fans that emit 2 square pulses per revolution.
TR Fan Tachometer Input TR = Revolution Time = 60/RPM (sec) TP = Pulse Time = T /2 R (Two Pulses Per Revolution) F = 32.786kHz / Divisor
TP Clock Source for Counter
FIGURE 8 - FAN TACHOMETER INPUT AND CLOCK SOURCE
The counter is used to determine the period of the Fan Tachometer input pulse. This counter, if reset on the rising edge of the fan tachometer input pulse, measures the number of clock pulses generated by the clock source for the duration of one fan tachometer input pulse. Since two fan tachometer input pulses are generated per revolution of the fan rotor, the speed of the fan is easily calculated. Everytime the fan tachometer input resets the counter, it also latches the value of the counter into the Fan Tachometer register. This value is used by the operating system to monitor the speed of the fan.
Fan Monitoring Logic The clock source for the counter is the output of the programmable divider whose input is the 32.768kHz oscillator (see figure below).
The counter is reset by the rising edge of each fan tachometer input pulse, by itself if it reaches its' maximum count of 0xFF, or by writing to the preload register. If the fan is functioning, a value is preloaded into the counter on the rising edge of the Fan Tachometer input. The counter counts the number of clock pulses generated for the duration of one Fan Tachometer input pulse. This value (Count) is then stored into the Fan Tachometer register. If the fan is operating at 70% (or less) of the maximum capacity, the Count value will be greater than or equal to 192 and thereby generate a PME# signal. To ensure the Fan Tachometer register has been updated if the fan suddenly seizes, a second PME is generated when the counter reaches 0xFF and the Fan Tachometer register is latched again. The Fan Tachometer register will remain at this value until another Fan Tachometer input pulse is received. A representation of the logic for the fan tachometer implementation is shown below.
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Preload
32kHz
Programmable Divider 1, 2, 4, 8
Counter Logic to generate PME event Latch Fan Tach Register on Fan Tach input pulse or Counter=0xFF
Note: If the fan is working the Fan Tachometer register will be latched by the Fan Tachometer input. If the fan fails, the first time the overflow bit is generated the Fan Tachomter register will be updated. The Fan Tachometer Registerwill not be updated again until after the Fan Tachometer input resets the counter.
FIGURE 9 - CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC Fan Tachometer Register The Fan Tachometer registers are used to store the value of the counter that monitors the speed of the associated fan. This value may be used by the operating system to monitor how the fan is functioning.
The ACPI BIOS polls this register periodically to determine the speed at which the fan rotor is revolving. See the Metalious ACPI/Manageability Specification, v1.0, dated April 30, 1999. The BIOS looks for particular values in this register to determine the rate at which the fan is functioning. (i.e. Count = FFh; means the fan has stopped). Since the count value must correspond to a particular rate of functioning, the Preload register is used to offset any differences. Therefore, the equation below has been derived to calculate the desired values for Count.
The fan count is determined according to the following equation: Count = 1 2 x 1.966 x 106 RPM x Divisor + Preload (Equation 1)
(Term 1)
In addition to the ACPI BIOS polling the register, a PME or SMI is generated at a count of 192, if enabled through the PME or SMI enable register, which corresponds to the "upper limit" for the fan count. This value is made to correspond to the "lower limit" of the RPM for the fan by programming the divisor and preload value accordingly. Typical practice is to consider 70% of normal RPM a fan failure.
Fan Preload Register The preload value is programmable via the FAN1 Preload Register and FAN2 Preload Register. The preload is the initial value for the fan count, which is used to adjust the count such that the value of 192 corresponds to the "lower limit" of the RPM. By setting the preload value and divisor properly, a PME or SMI will be generated when the RPM reaches the percentage of the nominal RPM that indicates a fan failure.
Notice in the examples shown below the Preload value was determined to be 32 for a fan that normally operates at 4400 RPMs. This preload value was determined for the case that a PME should be initiated at 70% of normal operation. A PME is generated when the counter reaches 192, but at 70% in this example only 160 counts are generated during one Fan Tachometer input pulse leaving a difference of 32.
Examples Term 1 in the equation above is 1/2 of the value determined by multiplying the clock source of 32.768kHz by 60sec/min and dividing by the product of the revolutions per minute times the divisor. The factor of 1/2 in Term 1 corresponds to two pulses per revolution. The default divisor, located in the Fan Control Register, is two. This results
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in a value for Term 1 in Equation 1 of 111.70 (~112) for a 4400 RPM. desired functionality.
The following tables show examples of the
Note: All calculations of Count were based on tachometer inputs with two pulses per revolution and on the clock source input divided down by two (default settings). RPM Time per Revolution 13.64 ms 19.48 ms 22.73 ms 27.22 ms Term 1 for "Divide by 2" (Default) in Decimal 112 counts 160 counts 186 counts 223 counts Preload Count = (Term 1) + Preload 144 192 218 255 (maximum count) Comments
4400 3080 2640 2204
32 32 32 32
Typical RPM 70% RPM 60% RPM 50% RPM
The divisor for each fan is programmable via the Fan Control Register, Logical Device A, runtime register 0x58. The choices for the divisor are 1, 2, 4 and 8. The default value is 2.
Mode Select Nominal RPM Time per Revolution Preload Counts for the Given Speed in Decimal 144 144 144 144 70% RPM Time per Revolution for 70% RPM 9.74 ms 19.48 ms 38.96 ms 77.92 ms
Divide by 1 Divide by 2 Divide by 4 Divide by 8
8800 4400 2200 1100
6.82 ms 13.64 ms 27.27 ms 54.54 ms
32 32 32 32
6160 3080 1540 770
7.16 SECURITY FEATURE
The following register describes the functionality to support security in the LPC47M192.
7.16.1 GPIO DEVICE DISABLE REGISTER CONTROL
The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to `01', selects the DDRC function for the GP43 pin. When bits[3:2]=01 the GP43 pin is an input, with non-inverted polarity. Bits[3:2] cannot be cleared by writing to these bits; they are cleared by VTR POR, VCC POR and PCI Reset. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a VCC POR, PCI reset or VTR POR. When the DDRC function is selected for GP43, the Device Disable register is controlled by the value of the GP43 pin as follows: If the GP43 pin is high, the Device Disable Register is Read-Only. If the GP43 pin is low, the Device Disable Register is Read/Write.
7.16.2 DEVICE DISABLE REGISTER
The Device Disable Register is located in the PME register block at offset 0x22 from the PME_BLK base I/O address in logical device A. Writes to this register are blocked when the GP43 pin is configured for the Device Disable Register Control function (GP43 configuration register bit 2 =1) and the GP43 pin is high. The configuration register for the device disable register is defined in the "Runtime Registers" section.
7.17 GAME PORT LOGIC
The LPC47M192 implements logic to support a dual game port. This logic includes the following for each game port: two 555 timers, two game port RC constant inputs (x-axis and y-axis), two game port button inputs and game port interface logic. The implementation of the Game Port uses a simple A/D converter constructed from a 555 timer to digitize the analog value of a potentiometer for the x-axis and y-axis of the joystick.
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The figure below illustrates the implementation of the game port logic in the LPC47M192.
Internal To LPC47M192
556 OUT1A TIM1A OUT1B TIM1B JOYW TRIG1A TRIG1B D0 D1 D2 JOYR Game Port Register D3 556 OUT2A TIM2A OUT2B TIM2B TRIG2A TRIG2B D4 D5 D6 D7 J1B1 J1B2 J2B1 J2B2 J2Y Y-Axis Vcc = 5V J2X X-Axis J1Y Y-Axis J1X X-Axis
Internal To Joysticks
Vcc = 5V Joystick 1 Vcc = 5V
Vcc = 5V Joystick 2 Vcc = 5V
Joystick 1 Button 1 Joystick 1 Button 2 Joystick 2 Button 1 Joystick 2 Button 2
Game software will write a byte to the game port to reset it, and then poll (read) the port until the x and y-axis RC time constant pins (TIMA,B) time out (return to zero). The elapsed time indicates the resistance value of the potentiometer and in turn, the position of the joystick. The figure below illustrates the timing of the game port signals. The 556 timers will reset the outputs (OUTA,B) to zero and the RC constant (TIMA,B) pins to zero when the RC constant (TIMA,B) inputs reach 2/3 of VREF as shown. VREF is the voltage on pin 44, which is either 5V or 3.3V. See the "VREF Pin " section.
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JOYW VREF
2 VREF 3
TIMA,B
t1
OUTA,B
JOYR
The game port register is defined below. It is a runtime register located at the address programmed into the base I/O address (GAME_PORT) in Logical Device 9.
Note: Register 0x60 is the high byte; 0x61 is the low byte. For example, to set the primary base address to 1234h, write 12h into 0x60, and 34h into 0x61.
When the activate bit in Logical Device 9 is cleared, it prevents the base I/O address for the game port from being decoded.
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Game Port Register Register Location: Default Value: Attribute: Size: D7 Button #2 Joystick 2 (J2B2)
+0h 00h Read-Only 8-bits
D5 Button #2 Joystick 1 (J1B2) D4 Button #1 Joystick 1 (J1B1)
System on
I/O Space VTR POR
D6 Button #1 Joystick 2 (J2B1)
D3 Y-Axis Joystick 2 (OUT2B)
D2 X-Axis Joystick 2 (OUT2A)
D1 Y-Axis Joystick 1 (OUT1B)
D0 X-Axis Joystick 1 (OUT1A)
The game port register is a read-only register. However, writing to the game port resets the RC time constant pins (TIMA,B) to zero. The reset of the time constant pins occur on the "back" edge of the write signal (when the write signal goes from its active state to its inactive state). The game port read (JOYR) will be an IO read to the address programmed into the base IO address in Logical Device 9. The game port write (JOYW) will be an IO write to the address programmed into the base IO address in Logical Device 9.
Minimum Rise Time The fastest rise time on the RC constant pins (minimum RC time constant) for the game port is 20usec.
7.17.1 POWER CONTROL REGISTER
Bit 2 in the Power Control Register (CR22) is the power control bit for the game port. This bit has the same function as the activate bit for logical device 9 and shadows the activate bit. The activate bit also shadows the power control bit 2.
7.17.2 VREF PIN
The LPC47M192 has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply. It is used for the game port. The reference voltage is used in the game port logic so that the joystick trigger voltage is 2/3 VREF where VREF is either 5V or 3.3V. This is to preserve joystick compatibility by maintaining the RC time constant reset trigger voltage of 3.3V (nominal) with VREF=5V (nominal), if required.
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7.18 Hardware Monitoring Interface
The Hardware Monitoring Block is a standalone block in the 2. It can be accessed using SMBus interface. This block is used to monitor +1.5, +1.8, +2.5V, +3.3V, +5V, +12V and Vccp (core processor) voltages. It can also monitor its own internal HVCC or HVSB. The block can be used to measure internal temperature and two external temperatures and diode faults. It can indicate out-of-limit temperature and voltage conditions. The block has an ability to output 20ms low pulse.
7.18.1 HARDWARE MONITORING INTERFACE SIGNAL DEFINITION
The following table shows the pins required for the Hardware Monitoring Block.
PIN NAME SDA TYPE Digital I/O (Open Drain) Digital Input DESCRIPTION System Management Bus bi-directional Data. output.
Open Drain
SCLK HVSS HVCC
System Management Bus Clock. Internally connected to all of the Hardware Monitoring Block circuitry. +3.3V VCC pin dedicated to the Hardware Monitoring block. Can be powered by +3.3V Standby power if monitoring in low power states is required. Voltage supply readout from the processor. This value is read in the VID Register. Voltage supply readout from the processor. This value is read in the VID Register. Voltage supply readout from the processor. This value is read in the VID Register. Voltage supply readout from the processor. This value is read in the VID Register. This is the negative input (current sink) from the remote thermal diode. This serves as the negative input into the A/D. If held high at power-up, initiates XNOR chain test mode. This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. See D0- pin description. See D0+ description. Defaults to Analog Input for +12V. Optionally, can be configured to read the VID4 pin, a voltage supply readout from the processor. This value is read in the VID4 Register. Analog input for +5V Analog input for +3.3V Analog input for +2.5V Analog input for +1.8V Analog input for +1.5V Analog input for +Vccp (processor voltage: 0 to 3.0V). The lowest order programmable bit of the SMBus Address. Can also be configured to be a minimum 20msec low Reset output pulse, or as an interrupt output for temperature and voltage interrupts. This pin functions as an output when the Hardware Monitor Block is in XNOR-Chain test mode.
Analog Ground Power
VID0 VID1 VID2 VID3 D0-/XNOR_IN
Digital Input Digital Input Digital Input Digital Input Analog Input/ Digital Input Analog Input Analog Input Analog Input Analog Input/ Digital Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital I/O (Open Drain)
D0+ D1D1+ 12V_IN/VID4
+5V_IN +3.3V_IN +2.5V_IN +1.8V_IN +1.5V_IN +Vccp_IN A0/RESET#/ THERM#/XNOR_OUT
7.18.2 SMBUS INTERFACE
The host processor communicates with the Hardware Monitor Block through a series of read/write registers via the SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral devices. The SMBus protocol includes a physical layer based on the I2CTM serial bus.
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The default power on SMBus address is 010110x binary, where x reflects the state defined by the A0 pin. The A0/RESET#/THERM#/XNOR_OUT pin requires an external pullup resistor if the RESET# or THERM# functions are used. This limits the SMBus address to 0101101 unless external circuitry is used to override the pull-up at power-up.
7.18.2.1 SMBus Slave Interface The Hardware Monitor Block SMBus implementation is a subset of the SMBus interface to the host. The Hardware Monitor Block is a slave-only SMBus device. The implementation in the Hardware Monitor Block is a subset of SMBus since it only supports four protocols.
The Read Byte, Receive Byte, Write Byte and Send Byte protocols are the only valid SMBus protocols for the Hardware Monitor Block. The part responds to other protocols as described in the Invalid Protocol Section. Reference the System Management Bus Specification, Rev 1.1. The SMBus interface is used to read and write the registers in the Hardware Monitor Block. The only valid registers for a read or write protocol are the registers shown in the Registers Section.
7.18.2.1.1 Bus Protocols Typical Write Byte, Read Byte, Send Byte and Receive Byte protocols are shown below. Register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates the Hardware Monitor Block driving data on the SDA line; otherwise host data is on the SDA line.
The slave address is the unique SMBus Interface Address for the Hardware Monitor Block that identifies it on SMBus. The register address field is the internal address of the register to be accessed. The register data field is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read. Data bytes are transferred MSB first. When using the Hardware Monitor Block SMBus Interface, a write will always consist of the SMBus Interface Address byte, followed by the Internal Address Register byte, then the data byte. There are two cases for a read: 1. The normal read protocol consists of a write to the Hardware Monitor Block with the SMBus Interface Address byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of the SMBus Interface Address byte, followed by the data byte read from the Hardware Monitor Block. This can be accomplished by using the Read Byte protocol or by using the Send Byte protocol followed by the Receive Byte protocol. 2. If the Internal Address Register is known to be at the desired Address, simply read the Hardware Monitor Block with the SMBus Interface Address byte, followed by the data byte read from the Hardware Monitor Block. This corresponds to the Receive Byte protocol.
Write Byte The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in Table 1 is performed correctly. Only one byte is transferred at time for a Write Byte protocol. Table 57 - SMBus Write Byte Protocol FIELD: Bits: START SLAVE ADDR 7 WR ACK REG. ADDR 8 ACK REG. DATA 8 ACK STOP
1
1
1
1
1
1
Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 2 is performed correctly. Only one byte is transferred at time for a Read Byte protocol.
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Table 58 - SMBus Read Byte Protocol FIELD: Bits: START SLAVE ADDR 7 WR ACK REG. ACK ADDR 8 1 START SLAVE ADDR 7 RD ACK REG. DATA 8 NACK STOP
1
1
1
1
1
1
1
1
Send Byte The Send Byte protocol is used to set the Internal Address Register to the correct register in the Hardware Monitor Block. No data is transferred for a Send Byte protocol. The Send Byte can be followed by the Receive Byte protocol described below in order to read data from the register. The send byte protocol cannot be used to write data - if data is to be written to a register then the write byte protocol must be used as described in subsection above. The send byte protocol is shown in the table below. Table 59 - SMBus Send Byte Protocol FIELD: Bits: START SLAVE ADDR 7 WR ACK REG. ADDR 8 ACK STOP
1
1
1
1
1
Receive Byte The Receive Byte protocol is used to read data from the registers when the register address is known to be at the desired address (using the Internal Address Register). This is used when the register address has been written to the desired address using the Send Byte protocol. This can be used for successive reads of the same register. The data will only be read if the protocol shown in Table 4 is performed correctly. Only one byte is transferred at time for a Receive Byte protocol. Table 60 - SMBus Receive Byte Protocol FIELD: START Bits: SLAVE ADDR 7 RD ACK REG. DATA 8 NACK STOP
1
1
1
1
1
7.18.2.1.2 Slave Address The slave address is the unique address for the Hardware Monitor Block that identifies the device on SMBus.
The Hardware Monitor Block's slave address is determined by the level on the A0 pin. The level on this pin forms the LSB of the 7-bit address 0101_10x. This pin may be used to support up to 2 Hardware Monitor Blocks in a given system. The upper 6 bits of the Hardware Monitor Block's slave address are hardwired in the Hardware Monitor Block.
7.18.2.1.3 Invalid Protocol Response Behavior Registers that are accessed with an invalid protocol will not be updated. A register will only be updated following a valid protocol. The only valid protocols are the read byte, receive byte and write byte protocols described above.
The only valid slave address is determined by the level on the A0 pin as the LSB of the address 0101_10x. The only valid registers for a read or write protocol are the registers shown in the Registers Section. Reserved registers are not considered valid registers. Attempting to communicate with the Hardware Monitor Block over SMBus with an invalid slave address, invalid register address or invalid protocol will result in no response, and the SMBus Slave Interface will return to the idle state.
7.18.2.1.4 General Call Address Response The Hardware Monitor Block will not respond to a general call address of 0000_000.
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7.18.2.1.5 Slave Device Time-Out The device will not time-out when SCLK is held low longer than TTIME-OUT Min = 25ms. 7.18.2.1.6 Stretching the SCLK Signal The Hardware Monitor Block supports stretching of the SCLK by other devices on the SMBus. The Hardware Monitor Block does not stretch the SCLK.
7.18.2.1.7 SMBus Timing The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the "Timing Diagram" section.
7.18.2.1.8 Bus Reset Sequence The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP field.
7.18.2.1.9 SMBus Alert Response Address The Hardware Monitor Block implements the SMBALERT# signal. The THERM# interrupt pin can be used as the SMBALERT#. SMBALERT# is used in conjunction with the SMBus General Call Address, 0001 100.
The Hardware Monitor Block device can signal the host that it wants to talk by pulling the SMBALERT# low. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte operation with the Alert Response Address (ARA). The Hardware Monitor Block, which pulled SMBALERT# low, will acknowledge the Alert Response Address and respond with its device address. The host performs a modified Receive Byte operation with the alert response address. The 7-bit device address provided by the Hardware Monitor Block device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one.
Table 61 - Modified SMBus Receive Byte Protocol Response to ARA FIELD: Bits: START ALERT RESPONSE ADDRESS 7 RD ACK HW MONITOR BLOCK SLAVE ADDRESS 8 NACK STOP
1
1
1
1
1
After acknowledging the slave address, the Hardware Monitor Block must disengage its SMBALERT# pulldown. If the condition that caused the interrupt remains, the Hardware Monitor Block will reassert the SMBALERT# on the next monitoring cycle.
7.18.3 HARDWARE MONITORING BLOCK
The following sub-sections describe the Hardware Monitoring Block.
7.18.3.1 Input Monitoring The Hardware Monitor Block's monitoring function is started by writing a `1' to the START bit in the Configuration Register (0x40). Measured values from the analog inputs and temperature sensors are stored in the Value Registers. These values can be compared to the programmed limits in the Limit Register via SMBus interface. The out-of-limit and diode fault conditions are stored in the Interrupt Status Registers. 7.18.3.2 Resetting the Hardware Monitoring Block
7.18.3.2.1 Power On Reset All the registers in the Hardware Monitor Block reset to a default value when power is applied to the block. The default state of the register is shown in the table in the Register Summary subsection. The default state of Value or Limit Registers are not shown because these registers have indeterminate power on values. Usually the first action after power up is to write limits into the Limit Registers.
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7.18.3.2.2 Soft Reset Setting bit 7 of the Configuration Register (0x40) performs a soft reset. This bit is self-clearing. Soft Reset performs reset on all the registers except the Value and Limit Registers. 7.18.3.3 Reset Out Pin The RESET# function is multiplexed on A0/RESET#/THERM#/XNOR_OUT pin. Upon power up, the Hardware Monitor Block reads this pin as an address pin (low bit of the SMBus address). The Hardware Monitor Block latches the value of this pin as the low order bit of the SMBus address.
A reset pulse output function can be selected by writing a `1' to bit 7 of the VID Register (0x47). If bit 4 (Reset) of Configuration Register (0x40) is set, RESET# pin will output a minimum 20ms low pulse. The Reset bit is selfclearing. The RESET# pin is open-drain and requires an external pullup resistor. If more than one Hardware Monitor Block is used on a system, only one can have this function enabled at one time since this will limit the SMBus address to 0101101, unless external circuitry is provided.
7.18.3.4 Monitoring Modes The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode. These modes are selected using bit 1 of the Special Function Register (0x4F). The following subsections contain a description of these monitoring modes.
For each mode, there are two options for the number of measurements that are performed on each temperature and voltage reading. These options are selected using bit 5 of the special function register (0x4F). These options are as follows: 1. 128 measurements are averaged for the remote diode temperature reading and 8 measurements are averaged for all voltage and the internal temperature reading. This is the default operation. 2. 16 measurements are averaged for the remote diode temperature reading and a single measurement is taken for all voltage and the internal temperature reading (i.e., no averaging). This is a power saving option. For option 1, the block performs a total of (2 x 128) + (1 x 8) + (8 x 8) = 328 conversions. (8 less if the 12V input is not selected i.e. 320). Option 2 reduces the number of conversions to (2 x 16) + (1 x 1) + (8 x 1) = 41 (or 40 if the 12V input is not selected). Each temperature conversion takes 1.688ms approx. and each voltage conversion takes 1.511ms approx. The total time for option 1 (328 conversions) is (2x128x1.688ms) + (1x8x1.688ms) + (8x8x1.511ms) = 542.336ms. The total time for option 2 (41 conversions) is (2x16x1.688ms) + (1x1x1.688ms) + (8x1x1.511ms) = 67.792ms.
7.18.3.4.1 Continuous Monitoring Mode In the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the Start bit is set high. The time for each voltage and temperature reading is shown above for each measurement option.
The continuous monitoring function is started by doing a write to the Configuration Register, setting the Start bit (Bit 0) high. The part then performs a "round robin" sampling of the inputs, in the order shown below (corresponding to locations in the Value RAM). Sampling of all values occurs in 542.336 ms (or 67.792ms - see above).
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SAMPLING ORDER 1 2 3 4 5 6 7 8 9 10 11
REGISTER Remote Diode Temp Reading 1 Ambient Temperature reading HVCC/+3.3HVSB reading +12V (If selected) reading +5V reading +3.3V reading +2.5V reading Vccp (processor) reading Remote Diode Temp Reading 2 +1.8V reading +1.5V reading
When the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every 542.336 ms (or 67.792ms - see above). Each measured value is compared to values stored in the Limit registers. When the measured value violates (or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers. The results of the sampling and conversions can be found in the Value RAM and are available at any time.
7.18.3.4.2 Cycle Monitoring Mode In cycle monitoring mode, the part completes all sampling and conversions, then waits to repeat the process. It repeats the sampling and conversion process every second (1.4 sec max). The sampling and conversion of each voltage and temperature reading is performed once every monitoring cycle. This is a power saving mode.
The cycle monitoring function is started by doing a write to the Configuration Register, setting the Start bit (Bit 0) high. The part then performs a "round robin" sampling of the inputs, in the order shown above. When the cycle monitoring function is started, it cycles through each measurement in sequence, and it performs a single conversion for each voltage and temperature approximately once every second. Each measured value is compared to values stored in the Limit registers. When the measured value violates (or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers The results of each sampling and conversion can be found in the Value RAM and are available at any time, however, they are only updated once every 1-1.4 seconds.
7.18.3.5 Interrupt Status Registers The Hardware Monitor Block contains a pair of interrupt status registers. These registers are used to reflect the state of all temperature and voltage out-of-limit/equal-limit error conditions and diode fault conditions that the Hardware Monitor Block monitors for. When an error occurs during the conversion cycle, its corresponding bit is set in its respective interrupt status register. The status register bits are updated continuously through each monitoring cycle. If a measurement is within (and not equal to) limits or if there is no diode fault, the corresponding status register bit will be cleared to `0'. If the measurement is equal to the limit value or out of limit or if there is a diode fault, the corresponding status register bit will be set to `1'. The diode fault conditions are described in the "External Temperature Measurement" section. Reading the status register does NOT clear its contents. These registers default to 0x00 on HVCC POR and Initialization. 7.18.3.6 Low Power Modes The Hardware Monitor Block can be placed in a low-power mode by writing a `0' to the Configuration Register (0x40). The low power mode that is entered is either sleep mode or shutdown mode as selected using bit 0 of the Special Function Register (4F). These modes do not reset any of the registers of the Hardware Monitor Block.
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7.18.3.6.1 Sleep Mode This is a low power mode in which bias currents are `on' but the Hardware Monitor Block is not operating. In this mode, the A/D converter and monitoring cycle will be turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode. 7.18.3.6.2 Shutdown Mode This is a low power mode in which bias currents are `off' and the Hardware Monitor Block is not operating. In this mode, the A/D converter and monitoring cycle will be turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode. 7.18.3.7 Analog Voltage Measurement The Hardware Monitor Block contains inputs for directly monitoring the power supplies (+12 V, +5 V, +3.3V, +2.5V, +1.8V, +1.5V, +Vccp and HVCC or HVSB). These inputs are scaled internally to a internal reference source, converted via a 8 bit successive approximation register ADC or a Delta-Sigma ADC (Analog-to-Digital Converter), and scaled such that the correct value refers to 3/4 scale or 192 decimal (except the Vccp input). This removes the need for external resistor dividers and allows for a more accurate means of measurement since the voltages are referenced to a known value. The 1.5V input does not have an internal resistor divider. Since these inputs are above Vcc and below Ground, they are not diode protected to the power rails. The measured values are stored in the Reading registers and compared with the Limit registers. The status bits in the Interrupt Status Register 1 and the Interrupt Status Register 2 are set if the measured values are outside (or equal to) the programmed limits.
The Vccp voltage input measures the processor voltage, which will lie in the range of 0V to 3.0V. The following table shows the values of the analog inputs that correspond to the min and max output codes of the A/D converter. For a complete list of the ADC conversions see Table 78 in Appendix B.
Input Voltage Min Value (Corresponds to A/D output 00000000) Max Value (Corresponds to A/D output 11111111) +12VIN <0.062 +5VIN <0.026 VCC/3.3VIN <0.017 +2.5VIN <0.013 +1.8VIN <0.009 +1.5VIN <0.008 +VCCP <0.012
>15.938
>6.640
>4.383
>3.320
>2.391
>1.992
>2.988
7.18.3.8 Voltage ID VID0-VID4 digital inputs are used to store processor Voltage ID codes (for processor operating voltage) in the VID and VID4 registers (0x47 and 0x49). These VIDs can be read out by the management system using the SMBus interface. Bits[3:0] in VID register is used for VID3 to VID0 inputs and Bit[0] of VID4 register is used for VID4 input. VID4 input is multiplexed with +12V_IN analog input. This pin defaults to the +12V_IN analog input at power up and bit 0 in VID4 register defaults to 0. This pin can be selected for VID4 by setting bit 5 in the Configuration Register (0x40). 7.18.3.9 Temperature Measurement Temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor pins (for measuring two external temperatures). See subsections below.
7.18.3.9.1 Internal Temperature Measurement Internal temperature can be measured by bandgap temperature sensor. The measurement is converted into digital format by internal ADC. This data is converted in two's complement format since both negative and positive temperature can be measured. This value is stored in Ambient Temperature Reading register (0x27). If this value out-of-limit (or equal to) the programmed limits in Ambient Temperature High Limit register (0x39) and Ambient Temperature Low Limit register (0x3A), then the corresponding status bits in the Interrupt Status Registers are set.
7.18.3.9.2 External Temperature Measurement The Hardware Monitor Block also provides a way to measure two external temperatures using diode sensor pins (Dx+ and Dx-). The value is stored in the Remote Diode Temperature Reading 1 register (0x26) for D0+ and D0pins. The value is stored in the Remote Diode Temperature Reading 2 register (0x52) for D1+ and D1- pins. If this value is out-of-limit (or equal to) the programmed limits (for D0+ and D0- pins, or D1+ and D1- pins) in Remote
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Temperature High Limit 1 or 2 register and Remote Temperature Low Limit 1 or 2 register, then the Remote Temp Error 1 or 2 status bit is set in the Interrupt Status Register 1. There are Remote Diode Fault status 1 and 2 bits in the Status Register 2 (0x42). The LPC47M192 automatically sets the associated diode fault bit to 1 when there is an open circuit fault on the Remote x+ or Remote x- thermal diode input pins. The occurrence of either a short (D+ and D- shorted together) or open circuit fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding remote temp error bit to be set. This will cause the THERM# pin to become active if enabled. This same operation applies (including the diode fault bit getting set) for the following board design error conditions: D+ shorted to VCC, D- shorted to VCC, D+ shorted to ground. The diode fault bit will also be set if D- is shorted to ground, however, the part will give a valid temperature reading (with some error), so the out of limit bit will not be set and therefore the THERM# pin will not go active for this condition.. Before a remote diode conversion is updated, the status of the remote diode is checked. The temperature change is computed by measuring the change in Vbe at two different operating points of the diode to which the Dx+ and Dx- pins are connected. But accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on. See "Appendix A - Thermal Diode Parameters" for relationship between the non-ideality factor and the change in Vbe.
Note: Since digital boards can be electrically noisy environments that may interfere when measuring very small voltages from a remote diode sensor, special layout considerations should be made. See "Layout Considerations" below. 7.18.3.9.3 Temperature Data Format Temperature data can be read from the three temperature registers. One is the Ambient Temperature Reading register (0x27), the second is the Remote Diode Temperature Reading 1 register (0x26), and the third is the Remote Diode Temperature Reading 2 register (0x52).
The following table shows the corresponding format of the temperature digital data, represented by an 8-bit, two's complement word with an LSB equal to 1.0 0C.
Temperature +125 0C +25 0C +1.0 0C 0 0C -1.0 0C -25 0C -40 0C Digital Output 0111 1101 0001 1001 0000 0001 0000 0000 1111 1111 1110 0111 1101 1000
7.18.3.9.4 Offset Register Offset Register 1 is used for internal or remote temperature 1 reading. The Offset Register 1 (1Fh) contain a 2's complement value which is added (or subtracted if the number is negative) to the temperature reading. The default value in the offset register is zero, so initially zero is always added to the temperature reading. This offset register is configured for the external temperature channel by default. It may be switched to the internal channel by setting bit 4 of the Special Function Register to 1.
7.18.3.9.5 Second Offset Register The Offset Register 2 at 1Eh is for second remote diode temperature reading. This register contains a 2's complement value which is added (or subtracted if the number is negative) to the second external temperature reading. Note that the default value in the offset register is zero, so initially zero is always added to the second temperature reading. This offset register only applies to remote diode temperature reading 2. No configuration bit is required. 7.18.3.10 Thermal / Voltage Interrupt Pin The THERM# function is multiplexed on A0/RESET#/THERM#/XNOR_OUT pin. This function is used as an interrupt output for out-of-limit temperature events. It can also be enabled for out-of-limit voltage events.
SMSC DS - LPC47M192 Page 136 Rev. 03/30/05
DATASHEET
If the internal or remote temperature reading is not within the low or high temperature limits, THERM# will be active low. It will also be low for the diode pin conditions mentioned in the "External Temperature Measurement" section. The THERM# pin will remain low while any of the Ambient Temp Error bit or the Remote Temp Error bit in Interrupt Status 1 Register is set. The THERM# function can be selected by writing a `1' to bit 2 of the Special Function Register (0x4F). This pin is open-drain and requires an external pullup resistor. If more than one Hardware Monitor Block is used on a system, only one can have this function enabled at one time since this will limit the SMBus address to 0101101, unless external circuitry is provided. The THERM# pin can be enabled to indicate out-of-limit/equal-limit voltages. Bit 3 of the Special Function register (4Fh) is used to enable this option. When this bit is set, if one or more of the voltage readings is not within the low or high limits, THERM# will be active low. This pin will remain low while the associated voltage error bit (+2.5v_Error, Vccp_Error, +3.3v_Error, +5v_Error, +12v_Error, HVCC_Error, +1.5v_Error or +1.8v_Error) in the Interrupt Status Register 1 and Interrupt Status Register 2 is set. The THERM# pin defaults to supporting out-of-limit/equal-limit temperature events only. The THERM# pin will remain low until Interrupt Status Register 1 and 2 are read. If the temperature or voltage remains out of limit or equal to the limit, the THERM# will be re-asserted on the next monitoring cycle. THERM# can also be cleared by issuing an Alert Response Address Call. The THERM# pin may only become active while the monitor block is operational.
Implementation Note: In designs using the Hardware Monitor Block of the LPC47M192, all the remote thermal diode inputs must be properly terminated, even if one or both of the remote temperature sensor channels will not be used to actively monitor temperatures. These inputs should be terminated with a thermal diode, a transistor or a resistor. If the channel will never be used to monitor temperature, a resistor can used to allow for proper functioning of the nTHERM pin. See application note "Using the Hardware Monitor Feature in SMSC Super I/O Devices" for more information.
Unused Analog Voltage Channel inputs should not be left unconnected. This is good design practice, and it will guarantee proper functioning of the nTHERM pin, if the nTHERM pin is enabled to indicate voltage events. Any Analog Voltage Measurement Channel that will not be used to actively monitor a power supply must be pulled up to some nominal voltage. If the nTHERM pin is not enabled to indicate voltage events, unused Analog Voltage Channels may be grounded.
7.18.3.11 Input Safety Since the power supply voltages will appear directly at the pins (1.5V - 12V), small external series resistors such as 470 ohm to 1k ohm (see Note) should be put into the lines driving the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. This value should be kept as small as possible, since raising this resistor will start affecting the accuracy of the internal dividers. These resistors are recommended, but not necessary. Note: The analog input channels on the LPC47M192 are calibrated for 500 ohm resistors. These optional external resistors should not exceed 1k. 7.18.3.12 Layout Considerations To ensure accuracy when measuring analog signals, whether from a voltage divider or remote diode sensor, the analog components should be located physically as close to the hardware monitoring block as possible. The following is a list of precautions and suggestions to gain optimal performance from the hardware monitoring block.
1. 2.
Devices that are sources of noise, such as generators, data/address buses and CRTs should be kept as far away from the hardware monitoring block as possible. (Approximately 4 to 8 inches is adequate). The Dx+ and Dx- tracks should be kept close together, in parallel with grounded guard tracks on each side. Using wide tracks will help to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. See FIGURE 10.
GND D+ DGND
SMSC DS - LPC47M192 Page 137
10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil.
Rev. 03/30/05
DATASHEET
FIGURE 10 - SUGGESTED MINIMUM TRACK WIDTH AND SPACING
3.
To reduce the effects of noise on the Dx+ and Dx- signals, a 2.2nF capacitor may be place between these two leads.
Dx+
2.2nF
External Temperature Sensing Diode
Dx-
FIGURE 11 - USING A DIODE AS A REMOTE TEMPERATURE SENSING ELEMENT
4.
Place 0.1uF (ceramic) bypass and 20uF (electrolytic or tantalum) capacitors in parallel between the power supply (HVCC) and ground. They should be kept as close to the hardware monitoring block as possible.
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8
RUNTIME REGISTERS
The following registers are runtime registers in the LPC47M192. They are located at the address programmed in the Base I/O Address in Logical Device A (also referred to as the Runtime Register) at the offset shown. These registers are powered by VTR.
Table 62 - Runtime Register Block Summary REGISTER OFFSET (hex) 00 TYPE PCI RESET VCC POR VTR POR SOFT RESET REGISTER
R/W R R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R/W R R/W R R R
R/W
Note 1
-(Note 4) 0x03 -
-(Note 4) 0x03 -
0x00 0x00 0x00 0x00 0x00 0x00
(Note 5)
-(Note 4) -
PME_STS Reserved - reads return 0 PME_EN Reserved - reads return 0 PME_STS1 PME_STS2 PME_STS3 PME_STS4 PME_STS5 Reserved - reads return 0 PME_EN1 PME_EN2 PME_EN3 PME_EN4 PME_EN5 Reserved - reads return 0 SMI_STS 1 SMI_STS 2 SMI_STS3 SMI_STS4 SMI_STS5 Reserved - reads return 0 SMI_EN1 SMI_EN2 SMI_EN3 SMI_EN4 SMI_EN5 Reserved - reads return 0 MSC_STS Reserved - reads return 0 Force Disk Change Floppy Data Rate Select Shadow UART1 FIFO Control Shadow UART2 FIFO Control Shadow Device Disable Register GP10 GP11 GP12 GP13 GP14
Rev. 03/30/05
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27
0x00(Note 5) 0x00 0x00 0x00 0x00 0x00 0x02(Note 4) 0x00 0x00 0x00
(Note 5)
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x01 0x01 0x01 0x01 0x01
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R/W R/W R/W R/W R/W
SMSC DS - LPC47M192
DATASHEET
REGISTER OFFSET (hex) 28
TYPE
PCI RESET
VCC POR
VTR POR
SOFT RESET
REGISTER
R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R R R R
0x00 0x00 0x04 - Note 2 0x00 - Note 2 - Note 3 -
0x00 0x00 0x04 - Note 2 0x00 - Note 2 - Note 3 -
0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x05 0x04 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 Page 140
-
GP15 GP16 GP17 GP20 GP21 GP22 Reserved - reads return 0 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP36 GP37 GP40 GP41 GP42 GP43 GP50 GP51 GP52 GP53 GP54 GP55 GP56 GP57 GP60 GP61 Reserved - reads return 0 Reserved - reads return 0 GP1 GP2 GP3 GP4 GP5 GP6 Reserved - reads return 0 Reserved - reads return 0 Reserved - reads return 0 Reserved - reads return 0 Reserved - reads return 0
Rev. 03/30/05
29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55
SMSC DS - LPC47M192
DATASHEET
REGISTER OFFSET (hex) 56
TYPE
PCI RESET
VCC POR
VTR POR
SOFT RESET
REGISTER
R/W R/W R/W R R R/W R/W R/W R/W R/W R
-
-
0x00 0x00 0x50 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -
-
FAN1 FAN2 Fan Control Fan1 Tachometer Register Fan2 Tachometer Register Fan1 Preload Register Fan2 Preload Register LED1 LED2 Keyboard Scan Code Reserved - reads return 0
57 58 59 5A 5B 5C 5D 5E 5F 60-7F
Note 1: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high. Note 2: Bits [3:2] of this register are reset (cleared) on VCC POR and PCI Reset (and VTR POR). Note 3: Bit 3 of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR). Note 4: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared. Note 5: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0).
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DATASHEET
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address register for Logical Device A.
Table 63 - Runtime Register Block Description NAME REG OFFSET (hex) 00 DESCRIPTION
PME_STS Default = 0x00 on VTR POR
(R/W)
N/A PME_EN Default = 0x00 on VTR POR
01 (R) 02 (R/W)
Bit[0] PME_Status = 0 (default) = 1 Set when LPC47M192 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to PME_Status will clear it and cause the LPC47M192 to stop asserting nIO_PME, in enabled. Writing a "0" to PME_Status has no effect. Bits[7:0] Reserved - reads return 0 Bit[0] PME_En = 0 nIO_PME signal assertion is disabled (default) = 1 Enables LPC47M192 to assert nIO_PME signal Bit[7:1] Reserved PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET Bits[7:0] Reserved - reads return 0 PME Wake Status Register 1 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] Reserved (Note 7) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
N/A PME_STS1 Default = 0x00 on VTR POR
03 (R) 04 (R/W)
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NAME
PME_STS2 Default = 0x00 on VTR POR
REG OFFSET (hex) 05
DESCRIPTION
(R/W)
PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 3 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] DEVINT_STS (status of group SMI signal for PME) Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect.
PME_STS3 Default = 0x00 on VTR POR
06 (R/W)
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NAME
PME_STS4 Default = 0x00 on VTR POR (Note 6)
REG OFFSET (hex) 07
DESCRIPTION
(R/W)
PME_STS5 Default = 0x00 on VTR POR (Note 6)
08 (R/W)
N/A
09 (R)
PME Wake Status Register 4 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP43 Bit[6] GP60 Bit[7] GP61 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. PME Wake Status Register 5 This register indicates the state of the individual PME wake sources, independent of the individual source enables or the PME_En bit. If the wake source has asserted a wake event, the associated PME Wake Status bit will be a "1". Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Status register is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a "1" to Bit[7:0] will clear it. Writing a "0" to any bit in PME Wake Status Register has no effect. Bits[7:0] Reserved - reads return 0
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NAME
PME_EN1 Default = 0x00 on VTR POR
REG OFFSET (hex) 0A
DESCRIPTION
(R/W)
PME_EN2 Default = 0x00 on VTR POR
0B (R/W)
PME Wake Enable Register 1 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] Reserved (Note 7) Bit[1] RI2 Bit[2] RI1 Bit[3] KBD Bit[4] MOUSE Bit[5] SPEKEY (Wake on specific key) Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Enable Register 2 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET.
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NAME
PME_EN3 Default = 0x00 on VTR POR
REG OFFSET (hex) 0C
DESCRIPTION
(R/W)
PME Wake Status Register 3 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME) Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. PME Wake Enable Register 4 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP43 Bit[6] GP60 Bit[7] GP61 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET.
PME_EN4 Default = 0x00 on VTR POR
0D (R/W)
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NAME
PME_EN5 Default = 0x00 on VTR POR
REG OFFSET (hex) 0E
DESCRIPTION
(R/W)
PME Wake Enable Register 5 This register is used to enable individual LPC47M192 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active ("1"), if the source asserts a wake event so that the associated status bit is "1" and the PME_En bit is "1", the source will assert the nIO_PME signal. When the PME Wake Enable register bit for a wake source is inactive ("0"), the PME Wake Status register will indicate the state of the wake source but will not assert the nIO_PME signal. Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or PCI RESET. Bits[7:0] Reserved - reads return 0 SMI Status Register 1 This register is used to read the status of the SMI inputs. The following bits must be cleared at their source. Bit[0] Reserved Bit[1] PINT. The parallel port interrupt defaults to `1' when the parallel port activate bit is cleared. When the parallel port is activated, PINT follows the nACK input. Bit[2] U2INT Bit[3] U1INT Bit[4] FINT Bit[5] MPU-401 INT Bit[6] Reserved Bit[7] Reserved (Note 7) SMI Status Register 2 This register is used to read the status of the SMI inputs. Bit[0] MINT. Cleared at source. Bit[1] KINT. Cleared at source. Bit[2] IRINT. This bit is set by a transition on the IR pin (IRRX or IRRX2 as selected in CR L5-F1-B6 i.e., after the MUX). Cleared by a read of this register. Bit[3] Reserved Bit[4] P12. Status bit is cleared by a write of `1'. The SMI event is cleared at source. Bit[7:5] Reserved
N/A SMI_STS1 Default = 0x02 on VTR POR Bit 1 is set to `1' on VCC POR, VTR POR, PCI RESET and SOFT RESET
0F (R) 10 (R/W)
SMI_STS2 Default = 0x00 on VTR POR
11 (R/W)
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NAME
SMI_STS3 Default = 0x00 on VTR POR
REG OFFSET (hex) 12
DESCRIPTION
(R/W)
SMI Status Register 3 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] Reserved Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP60 SMI Status Register 4 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP42 Bit[6] GP43 Bit[7] GP61 SMI Status Register 5 This register is used to read the status of the SMI inputs. The following bits are cleared on a write of `1'. Bit[0] GP54 Bit[1] GP55 Bit[2] GP56 Bit[3] GP57 Bit[4] Reserved Bit[5] Reserved Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 Bits[7:0] Reserved - reads return 0 SMI Enable Register 1 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] Reserved Bit[1] EN_PINT Bit[2] EN_U2INT Bit[3] EN_U1INT Bit[4] EN_FINT Bit[5] EN_MPU-401 INT Bit[6] Reserved Bit[7] Reserved (Note 7)
Page 148 Rev. 03/30/05
SMI_STS4 Default = 0x00 on VTR POR (Note 6)
13 (R/W)
SMI_STS5 Default = 0x00 on VTR POR
14 (R/W)
N/A SMI_EN1 Default = 0x00 on VTR POR
15 (R) 16 (R/W)
SMSC DS - LPC47M192
DATASHEET
NAME
SMI_EN2 Default = 0x00 on VTR POR
REG OFFSET (hex) 17
DESCRIPTION
(R/W)
SMI Enable Register 2 This register is used to enable the different interrupt sources onto the group nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pin, the serial IRQ stream or into the PME Logic. Unless otherwise noted, 1=Enable 0=Disable Bit[0] EN_MINT Bit[1] EN_KINT Bit[2] EN_IRINT Bit[3] Reserved Bit[4] EN_P12 Bit[5] EN_SMI_PME (Enable group SMI into PME logic) Bit[6] EN_SMI_S (Enable group SMI onto serial IRQ) Bit[7] EN_SMI (Enable group SMI onto nIO_SMI pin)
SMI_EN3 Default = 0x00 on VTR POR
18 (R/W)
SMI Enable Register 3 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] Reserved Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP60 SMI Enable Register 4 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP41 Bit[5] GP42 Bit[6] GP43 Bit[7] GP61
SMI_EN4 Default = 0x00 on VTR POR
19 (R/W)
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NAME
SMI_EN5 Default = 0x00 on VTR POR
REG OFFSET (hex) 1A
DESCRIPTION
(R/W)
SMI Enable Register 5 This register is used to enable the different interrupt sources onto the group nSMI output. 1=Enable 0=Disable Bit[0] GP54 Bit[1] GP55 Bit[2] GP56 Bit[3] GP57 Bit[4] Reserved Bit[5] Reserved Bit[6] FAN_TACH1 Bit[7] FAN_TACH2 Bits[7:0] Reserved - reads return 0 Miscellaneous Status Register Bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an edge occurs on the GP21 pin. Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an edge occurs on the GP22 pin. Bit[2] Either Edge Triggered Interrupt Input 2 Status. This bit is set when an edge occurs on the GP41 pin. Bit[3] Either Edge Triggered Interrupt Input 3 Status. This bit is set when an edge occurs on the GP43 pin. Bit[4] Either Edge Triggered Interrupt Input 4 Status. This bit is set when an edge occurs on the GP60 pin. Bit[5] Either Edge Triggered Interrupt Input 5 Status. This bit is set when an edge occurs on the GP61 pin. Bit[7:6] Reserved. This bit always returns zero. Bits[7:0] Reserved - reads return 0
N/A MSC_STS Default = 0x00 on VTR POR
1B (R) 1C (R/W)
N/A
1D (R)
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NAME
Force Disk Change Default = 0x03 on VCC POR, PCI Reset and VTR POR
REG OFFSET (hex) 1E
DESCRIPTION
(R/W)
Force Disk Change Bit[0] Force Disk Change for FDC0 0=Inactive 1=Active Bit[1] Force Disk Change for FDC1 0=Inactive 1=Active Force Change 0 and 1 can be written to 1 but are not clearable by software. Force Change 0 is cleared on nSTEP and nDS0 Force Change 1 is cleared on nSTEP and nDS1 DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG Setting either of the Force Disk Change bits active `1' forces the FDD nDSKCHG input active when the appropriate drive has been selected. Bit[7:2] Reserved
Floppy Data Rate Select Shadow
1F
(R)
Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] PRECOMP 0 Bit[3] PRECOMP 1 Bit[4] PRECOMP 2 Bit[5] Reserved Bit[6] Power Down Bit[7] Soft Reset UART FIFO Control Shadow 1 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB) UART FIFO Control Shadow 2 Bit[0] FIFO Enable Bit[1] RCVR FIFO Reset Bit[2] XMIT FIFO Reset Bit[3] DMA Mode Select Bit[5:4] Reserved Bit[6] RCVR Trigger (LSB) Bit[7] RCVR Trigger (MSB)
UART1 FIFO Control Shadow
20 (R)
UART2 FIFO Control Shadow
21 (R)
SMSC DS - LPC47M192
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DATASHEET
NAME
Device Register
Disable
Default = 0x00 VTR POR
If "0" (enabled), bits[7:3] have no effect on the devices; devices are controlled by their respective activate bits. Read/Write when If "1" (disabled), bits[7:3] override the activate bits in the configuration registers for each logical block. GP43 register Bit[0]: Floppy Write Protect. bits[3:2] = 01 0= no effect: floppy write protection is controlled by the AND write protect pin or the forced write protect bit (bit 0 of GP43 pin = 0 register 0xF1 in Logical Device 0); OR 1= Write Protected. GP43 register If set to 1, this bit overrides the write protect pin on the bits[3:2] 01 part and the forced write protect bit. READ-ONLY When GP43 register bits[3:2] =01 AND GP43 pin = 1 nWRTPRT (to the FDC Core) = (nDS0 AND Force Write Protect) OR (nDS1 AND Force Write Protect)OR nWRTPRT (from the FDD Interface) OR Floppy Write Protect
Note: The Force Write Protect bit is in the FDD Option configuration register.
REG OFFSET (hex) 22
DESCRIPTION
Bits[2:1]: Reserved. Return 0 on read. Bit[3]: Floppy Enable. 0=No effect: FDC controlled by its activate bit; 1=Floppy Disabled Bit[4]: MPU-401 Serial Port Enable. 0=No effect: MPU-401 UART controlled by its activate bit; 1=MPU-401 UART Disabled Bit[5]: Serial Port 2 Enable. 0=No effect: UART2 controlled by its activate bit; 1=UART2 Disabled Bit[6]: Serial Port 1 Enable. 0=No effect: UART1 controlled by its activate bit; 1=UART1 Disabled Bit[7]: Parallel Port Enable. 0=No effect: PP controled by its activate bit; 1=PP Disabled GP10 Default = 0x01 on VTR POR 23 (R/W) General Purpose I/0 bit 1.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=J1B1 (Joystick 1, Button 1) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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DATASHEET
NAME
GP11 Default = 0x01 on VTR POR
REG OFFSET (hex) 24
DESCRIPTION
(R/W)
GP12 Default = 0x01 on VTR POR
25 (R/W)
GP13 Default = 0x01 on VTR POR
26 (R/W)
GP14 Default = 0x01 on VTR POR
27 (R/W)
GP15 Default = 0x01 on VTR POR
28 (R/W)
General Purpose I/0 bit 1.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J1B2 (Joystick 1, Button 2) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J2B1 (Joystick 2, Button 1) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J2B2 (Joystick 2, Button 2) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J1X (Joystick 1, X-Axis RC Constant) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J1Y (Joystick 1, Y-Axis RC Constant) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
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DATASHEET
NAME
GP16 Default = 0x01 on VTR POR
REG OFFSET (hex) 29
DESCRIPTION
(R/W)
General Purpose I/0 bit 1.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J2X (Joystick 2, X-Axis RC Constant) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 1.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= J2Y (Joystick 2, Y-Axis RC Constant) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=8042 P17 function 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11= nDS1 - Floppy Drive Select 1 (Note 4) 10=Either Edge Triggered Interrupt Input 0 (Note 1), 01=8042 P16 function (User Note 2) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
GP17 Default = 0x01 on VTR POR
2A (R/W)
GP20 Default = 0x01 on VTR POR
2B (R/W)
GP21 Default =0x01 on VTR POR
2C (R/W)
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DATASHEET
NAME
GP22 Default =0x01 on VTR POR
REG OFFSET (hex) 2D
DESCRIPTION
(R/W)
General Purpose I/0 bit 2.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11= nMTR1 - Floppy Motor Select 1 (Note 4) 10=Either Edge Triggered Interrupt Input 1 (Note 1) 01=8042 P12 function (User Note 2) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bits[7:0] Reserved - reads return 0 General Purpose I/0 bit 2.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Reserved Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=MIDI_IN 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 2.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=MIDI_OUT 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
N/A GP24 Default = 0x01 on VTR POR
2E (R) 2F (R/W)
GP25 Default = 0x01 on VTR POR
30 (R/W)
GP26 Default = 0x01 on VTR POR
31 (R/W)
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DATASHEET
NAME
GP27 Default = 0x01 on VTR POR
REG OFFSET (hex) 32
DESCRIPTION
(R/W)
GP30 Default = 0x01 on VTR POR
33 (R/W)
General Purpose I/0 bit 2.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nIO_SMI (Note 5) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity :=1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN_TACH1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
GP31 Default = 0x01 on VTR POR
34 (R/W)
GP32 Default = 0x01 on VTR POR Default = 0x00 on VCC POR and PCI Reset (Note 3)
35 (R/W)
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DATASHEET
NAME
GP33 Default = 0x01 on VTR POR Default = 0x00 on VCC POR and PCI Reset (Note 3)
REG OFFSET (hex) 36
DESCRIPTION
(R/W)
GP34 Default = 0x05 on VTR POR
37 (R/W)
GP35 Default = 0x04 on VTR POR, VCC POR and PCI Reset (Note 3)
38 (R/W)
GP36 Default = 0x01 on VTR POR
39 (R/W)
General Purpose I/0 bit 3.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=FAN1 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IRRX2 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=IRTX2 (Note 2) 0=GPIO Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1= nKBDRST 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 3.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=A20M 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
Page 157 Rev. 03/30/05
GP37 Default = 0x01 on VTR POR
3A (R/W)
SMSC DS - LPC47M192
DATASHEET
NAME
GP40 Default =0x01 on VTR POR
REG OFFSET (hex) 3B
DESCRIPTION
(R/W)
General Purpose I/0 bit 4.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=DRVDEN0 (Note 4) 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 4.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 2 (Note 1) 01=DRVDEN1 (Note 4) 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 4.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[2] Alternate Function Select 1=nIO_PME Note: configuring this pin function as output with noninverted polarity will give an active low output signal. The output type can be either open drain or push-pull. 0=Basic GPIO function Bits[6:3] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
GP41 Default =0x01 on VTR POR
3C (R/W)
GP42 Default =0x01 on VTR POR
3D (R/W)
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DATASHEET
NAME
GP43 Default = 0x01 on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and PCI Reset
REG OFFSET (hex) 3E
DESCRIPTION
(R/W)
General Purpose I/0 bit 4.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Either Edge Triggered Interrupt Input 3 (Note 1) 10=Reserved 01=Device Disable Register Control. The GP43 pin is an input, with non-inverted polarity. When bits[3:2]=01, they cannot be changed by writing to these bits; they are cleared by VCC POR, PCI Reset and VTR POR. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a VCC POR, PCI Reset or VTR POR. The Device Disable register is controlled by the value of the GP43 pin as follows: If the GP43 pin is high, the Device Disable Register is Read-Only. If the GP43 pin is low, the Device Disable Register is Read/Write. 00=Basic GPIO function Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nRI2 (User Note 1) 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nDCD2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
GP50 Default = 0x01 on VTR POR
3F (R/W)
GP51 Default = 0x01 on VTR POR
40 (R/W)
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DATASHEET
NAME
GP52 Default = 0x01 on VTR POR
REG OFFSET (hex) 41
DESCRIPTION
(R/W)
GP53 Default = 0x00 on VTR POR, VCC POR and PCI Reset (Note 3)
42 (R/W)
General Purpose I/0 bit 5.2 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=RXD2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.3 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=TXD2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.4 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nDSR2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.5 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nRTS2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull
GP54 Default = 0x01 on VTR POR
43 (R/W)
GP55 Default = 0x01 on VTR POR
44 (R/W)
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DATASHEET
NAME
GP56 Default = 0x01 on VTR POR
REG OFFSET (hex) 45
DESCRIPTION
(R/W)
GP57 Default = 0x01 on VTR POR
46 (R/W)
GP60 Default = 0x01 on VTR POR
47 (R/W)
GP61 Default = 0x01 on VTR POR
48 (R/W)
N/A
49 - 4A (R)
General Purpose I/0 bit 5.6 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nCTS2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 5.7 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Reserved 01=nDTR2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.0 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 4 (Note 1) 01=LED1 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull General Purpose I/0 bit 6.1 Bit[0] In/Out : =1 Input, =0 Output Bit[1] Polarity : =1 Invert, =0 No Invert Bit[3:2] Alternate Function Select 11=Reserved 10=Either Edge Triggered Interrupt Input 5 (Note 1) 01=LED2 00=GPIO Bits[6:4] Reserved Bit[7] Output Type Select 1=Open Drain 0=Push Pull Bits[7:0] Reserved - reads return 0
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DATASHEET
NAME
GP1 Default = 0x00 on VTR POR
REG OFFSET (hex) 4B
DESCRIPTION
(R/W)
GP2 Default = 0x00 on VTR POR
4C (R/W)
GP3 Default = 0x00 on VTR POR Bits 2 and 3 are reset on VCC POR, PCI Reset and VTR POR GP4 Default = 0x00 on VTR POR
4D (R/W)
4E (R/W)
GP5 Default = 0x00 on VTR POR Bit 3 is reset on VCC POR, PCI Reset and VTR POR
4F (R/W)
GP6 Default = 0x00 on VTR POR N/A
50 (R/W) 51 - 55 (R)
General Purpose I/0 Data Register 1 Bit[0] GP10 Bit[1] GP11 Bit[2] GP12 Bit[3] GP13 Bit[4] GP14 Bit[5] GP15 Bit[6] GP16 Bit[7] GP17 General Purpose I/0 Data Register 2 Bit[0] GP20 Bit[1] GP21 Bit[2] GP22 Bit[3] Reserved Bit[4] GP24 Bit[5] GP25 Bit[6] GP26 Bit[7] GP27 General Purpose I/0 Data Register 3 Bit[0] GP30 Bit[1] GP31 Bit[2] GP32 Bit[3] GP33 Bit[4] GP34 Bit[5] GP35 Bit[6] GP36 Bit[7] GP37 General Purpose I/0 Data Register 4 Bit[0] GP40 Bit[1] GP41 Bit[2] GP42 Bit[3] GP43 Bit[7:4] Reserved General Purpose I/0 Data Register 5 Bit[0] GP50 Bit[1] GP51 Bit[2] GP52 Bit[3] GP53 Bit[4] GP54 Bit[5] GP55 Bit[6] GP56 Bit[7] GP57 General Purpose I/0 Data Register 6 Bit[0] GP60 Bit[1] GP61 Bit[7:2] Reserved Bits[7:0] Reserved - reads return 0
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DATASHEET
NAME
FAN1 Default=0x00 on VTR POR
REG OFFSET (hex) 56
DESCRIPTION
(R/W)
FAN2 Default = 0x00 on VTR POR
57 (R/W)
FAN Register 1 Bit[0] Fan Control 1=FAN1 pin is high 0=bits[6:1] control the duty cycle of the FAN1 pin. Bit[6:1] Duty Cycle Control for FAN1 Control the duty cycle of the FAN1 pin 000000 = pin is low 100000 = 50% duty cycle 111111 = pin is high for 63, low for 1 Bit[7] Fan 1 Clock Select This bit is used with the Fan 1 Clock Source Select and the Fan 1 Clock Multiplier bits in the Fan Control register (0x58) to determine the fan speed FOUT. See Table 56 in "Fan Speed Control and Monitoring" section. The fan speed may be doubled through bit 2 of Fan Control Register at 0x58. FAN Register 2 Bit[0] Fan Control 1=FAN2 pin is high 0=bits[6:1] control the duty cycle of the FAN2 pin. Bit[6:1] Duty Cycle Control for FAN2 Control the duty cycle of the FAN2 pin 000000 = pin is low 100000 = 50% duty cycle 111111 = pin is high for 63, low for 1 Bit[7] Fan 2 Clock Select This bit is used with the Fan 2 Clock Source Select and the Fan 2 Clock Multiplier bits in the Fan Control register (0x58) to determine the fan speed FOUT. See Table 56 in "Fan Speed Control and Monitoring" section. The fan speed may be doubled through bit 3 of Fan Control Register at 0x58.
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DATASHEET
NAME
Fan Control Default = 0x50 on VTR POR
REG OFFSET (hex) 58
DESCRIPTION
(R/W)
Fan1 Tachometer Register Default = 0x00 on VTR POR
59 (R)
Fan Control Register Bit[0] Fan 1 Clock Source Select This bit and the Fan 1 Clock Multiplier bit is used with The Fan 1 Clock Select bit in the Fan 1 register (0x56) to determine the fan speed FOUT. See Table 56 in "Fan Speed Control and Monitoring" section. Bit[1] Fan 2 Clock Source Select This bit and the Fan 2 Clock Multiplier bit is used with The Fan 2 Clock Select bit in the Fan 2 register (0x57) to determine the fan speed FOUT. See Table 56 in "Fan Speed Control and Monitoring" section. Bit[2] Fan 1 Clock multiplier 0=No multiplier used 1=Double the fan speed selected by bit 0 of this register and bit 7 of the FAN1 register Bit[3] Fan 2 Clock multiplier 0=No multiplier used 1=Double the fan speed selected by bit 1 of this register and bit 7 of the FAN2 register Bit[5:4] The FAN1 count divisor. Clock scalar for adjusting the tachometer count. Default = 2. 00: divisor = 1 01: divisor = 2 10: divisor = 4 11: divisor = 8 Bit[7:6] The FAN2 count divisor. Clock scalar for adjusting the tachometer count. Default = 2. 00: divisor = 1 01: divisor = 2 10: divisor = 4 11: divisor = 8 Fan Tachometer Register 1 Bit]7:0] The 8-bit FAN1 tachometer count. The number of counts of the internal clock per pulse of the fan. The count value is computed from Equation 1. This value is the final (maximum) count of the previous pulse (latched). The value in this register may not be valid for up to 2 pulses following a write to the preload register. Fan Tachometer Register 2 Bit[7:0] The 8-bit FAN2 tachometer count. The number of counts of the internal clock per pulse of the fan. The count value is computed from Equation 1. This value is the final (maximum) count of the previous pulse (latched). The value in this register may not be valid for up to 2 pulses following a write to the preload register. Fan Preload Register 1 Bit[7:0] The FAN1 tachometer preload. This is the initial value used in the computation of the FAN1 count. Writing this register resets the tachometer count.
Fan2 Tachometer Register Default = 0x00 on VTR POR Fan1 Register Preload
5A (R)
5B (R/W)
Default = 0x00 on VTR POR
SMSC DS - LPC47M192
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DATASHEET
NAME
REG OFFSET (hex) 5C
DESCRIPTION
Fan2 Register
Preload (R/W)
Fan Preload Register 2 Bit[7:0] The FAN2 tachometer preload. This is the initial value used in the computation of the FAN2 count. Writing this register resets the tachometer count.
Default = 0x00 on VTR POR LED1 Default = 0x00 on VTR POR
5D (R/W)
LED2 Default = 0x00 on VTR POR
5E (R/W)
Keyboard Code Default = 0x00 on VTR POR N/A
Scan
5F (R/W)
60-7F (R)
LED1 Bit[1:0] LED1 Control 00=off 01=blink at 1Hz rate with a 50% duty cycle (0.5 sec 0.5 sec off) 10=Blink at 1/2 HZ rate with a 25% duty cycle (0.5 sec 1.5 sec off) 11=on Bits[7:2] Reserved LED2 Bit[1:0] LED2 Control 00=off 01=blink at 1Hz rate with a 50% duty cycle (0.5 sec 0.5 sec off) 10=Blink at 1/2 HZ rate with a 25% duty cycle (0.5 sec 1.5 sec off) 11=on Bits[7:2] Reserved Keyboard Scan Code Bit[0] LSB of Scan Code ... ... ... Bit[7] MSB of Scan Code Bits[7:0] Reserved - reads return 0
on, on,
on, on,
User Note: When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be properly programmed, including in/out, polarity and output type. The polarity bit does not affect the DDRC function or the either edge triggered interrupt functions. User Note 1: If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register. User Note 2: In order to use the P12, P16 and P17 functions, the corresponding GPIO must be programmed for output, non-invert, and push-pull output type. Note 1: If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set the PME, SMI and MSC status bits. Note 2: The IRTX2 function can be used on this pin if the IR Location Mux bit in the Serial Port 2 IR Option register is set. Note 3: These pins default to an output and LOW on VCC POR and PCI Reset. Note 4: If the FDC function is selected on this pin (nMTR1, nDS1, DRVDEN0, DRVDEN1) then bit 6 of the FDD Mode Register (Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control Register. Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is selected. Note 5: The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable bit (EN_SMI, bit 7 of the SMI_EN2 register) is `0'. When the output buffer type is OD, nIO_SMI pin is floating when inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when inactive. Note 6: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be set on a VCC POR. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0). Note 7: These bits are R/W but have no effect on circuit operation.
SMSC DS - LPC47M192 Page 165 Rev. 03/30/05
DATASHEET
9
CONFIGURATION
The Configuration of the LPC47M192 is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47M192 is designed for motherboard applications in which the resources required by their components are known. With its flexible resource allocation architecture, the LPC47M192 allows the BIOS to assign resources at POST.
9.1
System Elements
9.1.1 PRIMARY CONFIGURATION ADDRESS DECODER
After a hard reset (PCI_RESET# pin asserted) or Vcc Power On Reset the LPC47M192 is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the LPC47M192 into Configuration Mode. The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only valid when the LPC47M192 is in Configuration Mode. The SYSOPT pin is latched on the falling edge of the PCI_RESET# or on Vcc Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at powerup. Once powered up the configuration port base address can be changed through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin which is shared with the GP24 signal on pin 45.
Note: An external pull-down resistor is required for the base IO address to be 0x02E for configuration. An external pull-up resistor is required to move the base IO address for configuration to 0x04E.
The INDEX and DATA ports are effective only when the chip is in the Configuration State. SYSOPT= 0 SYSOPT= 1 10k PULL-DOWN 10K PULL-UP RESISTOR RESISTOR PORT NAME CONFIG PORT (Note) 0x02E 0x04E INDEX PORT (Note) 0x02E 0x04E DATA PORT INDEX PORT + 1
Note: The configuration port base address can be relocated through CR26 and CR27.
TYPE Write Read/Write Read/Write
9.1.1.1 Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0x55> 9.1.1.2 Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = <0xAA>
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9.2
1) 2) 3)
Configuration Sequence
Enter Configuration Mode Configure the Configuration Registers Exit Configuration Mode
To program the configuration registers, the following sequence must be followed:
9.2.1 ENTER CONFIGURATION MODE
To place the chip into the Configuration State the Config Key is sent to the chip's CONFIG PORT. The config key consists of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Configuration State (The auto Config ports are enabled).
9.2.1.1 Configuration Mode The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports. In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX PORT address + 1. The desired configuration registers are accessed in two steps:
a) b)
Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then write the number of the desired logical device to the DATA PORT Write the address of the desired configuration register within the logical device to the INDEX PORT and then write or read the configuration register through the DATA PORT.
Note: If accessing the Global Configuration Registers, step (a) is not required.
9.2.2 EXIT CONFIGURATION MODE
To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State. Note: Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter the Configuration State.
9.2.2.1 Programming Example The following is an example of a configuration program in Intel 8086 assembly language.
;----------------------------. ; ENTER CONFIGURATION MODE | ;----------------------------` MOV DX,02EH MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, | ; LOGICAL DEVICE 8 | ;----------------------------` MOV DX,02EH MOV AL,07H OUT DX,AL ;Point to LD# Config Reg MOV DX,02FH MOV AL, 08H OUT DX,AL;Point to Logical Device 8 ; MOV DX,02EH MOV AL,E0H OUT DX,AL ; Point to CRE0 MOV DX,02fH MOV AL,02H OUT DX,AL ; Update CRE0 ;-----------------------------. ; EXIT CONFIGURATION MODE | ;-----------------------------` MOV DX,02EH MOV AX,0AAH OUT DX,AL
Notes: HARD RESET: PCI_RESET# pin asserted. SOFT RESET: Bit 0 of Configuration Control register set to one. All host accesses are blocked for 500s after Vcc POR (see Power-up Timing Diagram)
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Table 64 - LPC47M192 Configuration Registers Summary INDEX TYPE PCI RESET VCC POR VTR POR SOFT RESET CONFIGURATION REGISTER
0x02 0x03 0x07 0x20 0x21 0x22 0x23 0x24 0x26
W R R/W R R R/W R/W R/W R/W
0x00 0x00 0x60 0x00 0x00 0x44 Sysopt=0: 0x2E Sysopt=1: 0x4E Sysopt=0: 0x00 Sysopt=1: 0x00 -
GLOBAL CONFIGURATION REGISTERS 0x00 0x00 Config Control
0x00 0x60 0x00 0x00 0x44 Sysopt=0: 0x2E Sysopt=1: 0x4E Sysopt=0: 0x00 Sysopt=1: 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x60 0x00 0x00 0x44 -
0x00 0x60 0x00 -
Reserved - reads return 0 Logical Device Number Device ID - hard wired Device Rev - hard wired Power Control Power Mgmt OSC Configuration Port Address Byte 0 (Low Byte) Configuration Port Address Byte 1 (High Byte) Reserved TEST 6 TEST 4 TEST 5 TEST 1 TEST 2
Current Revision
0x27
R/W
-
-
0x28 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x60 0x61 0x70 0x74 0xF0 0xF1 0xF2 0xF4 0xF5
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x00 0x00 0x00
-
0x00 0x00 TEST 3 LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x00 0x00 0x00 0x00 Activate 0x03 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x03 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x03 0xF0 0x06 0x02 0x0E 0x00 0xFF 0x00 0x03 0xF0 0x06 0x02 Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select DMA Channel Select FDD Mode Register FDD Option Register FDD Type Register FDD0
0x30 0x60 0x61 0x70 0x74 0xF0 0xF1
R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x00 FDD1 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x00 0x00 0x00 0x00 Activate 0x00 0x00 0x00 0x04 0x3C 0x00 0x00 0x00 0x00 0x04 0x3C 0x00 0x00 0x00 0x00 0x04 0x3C 0x00
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0x00 0x00 0x00 0x04 -
Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select DMA Channel Select Parallel Port Mode Register Parallel Port Mode Register 2
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DATASHEET
INDEX
TYPE
PCI RESET
VCC POR
VTR POR
SOFT RESET
CONFIGURATION REGISTER
LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port 1)
0x30 0x60 0x61 0x70 0xF0 0x30 0x60 0x61 0x70 0xF0 0xF1 0xF2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x03
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x03
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x03
0x00 0x00 0x00 0x00 0x00 0x00 0x00 -
Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select Serial Port 1 Mode Register Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Primary Interrupt Select Serial Port 2 Mode Register IR Options Register IR Half Duplex Timeout
LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2)
LOGICAL DEVICE 6 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (Keyboard)
0x30 0x70 0x72 0xF0
R/W R/W R/W R/W
0x00 0x00 0x00 0x00 (Note 1)
0x00 0x00 0x00 0x00 (Note 1)
0x00 0x00 0x00 0x00
0x00 0x00 0x00 -
Activate Primary (Keyboard) Secondary (Mouse) Interrupt Interrupt Select Select
KRESET and GateA20 Select
LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 9 CONFIGURATION REGISTERS (Game Port)
0x30 0x60 0x61
R/W R/W R/W
0x00 0x00 0x00
0x00 0x00 0x00
0x00 0x00 0x00
0x00 0x00 0x00
Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte Activate Primary Base I/O Address High Byte Primary Base I/O Address Low Byte
LOGICAL DEVICE A CONFIGURATION REGISTERS (Runtime Registers)
0x30 0x60 0x61 0XF0 0x30 0x60, 0x61 0x70
R/W R/W R/W R/W R/W R/W R/W R/W
0x00 0x00 0x00 -
0x00 0x00 0x00 -
0x00 0x00 0x00 0X00 0x00 0x03 0x30 0x05
0x00 0x00 0x00 -
CLOCKI32 LOGICAL DEVICE B CONFIGURATION REGISTERS (MPU-401) 0x00 0x03 0x30 0x05 0x00 0x03 0x30 0x05 0x00 0x03 0x30 0x05 Activate MPU-401 Primary Address High Byte MPU-401 Primary Address Low Byte Primary Interrupt Select Base Base I/O I/O
Note: Reserved registers are read-only, reads return 0. Note 1. Bits[6:5] of KRESET and GateA20 Select register reset on VTR POR only.
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9.3
Chip Level (Global) Control/Configuration Registers [0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the selected register. These registers are accessible only in the Configuration Mode.
Table 65 - Chip Level Registers REGISTER ADDRESS DESCRIPTION Chip (Global) Control Registers 0x00 Reserved - Writes are ignored, reads return 0. 0x01 0x02 W The hardware automatically clears this bit after the write, there is no need for software to clear the bits. Bit 0 = 1: Soft Reset. Refer to the "Configuration Registers" table for the soft reset value for each register.
Config Control Default = 0x00 on VCC POR, VTR POR and PCI RESET
0x03 - 0x06 Reserved - Writes are ignored, reads return 0. Logical Device # 0x07 R/W A write to this register selects the current logical device. This allows access to the control and configuration registers for each logical device. Note: The Activate command operates only on the selected logical device.
Default = 0x00 on VCC POR, VTR POR, SOFT RESET and PCI RESET Card Level 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Reserved Chip Level, SMSC Defined 0x20 R Device ID A read only register which provides device identification. Bits[7:0] = 0x60 when read. Hard wired Default = 0x60 on VCC POR, VTR POR, SOFT RESET and PCI RESET Device Rev Hard wired = Current Revision PowerControl Default = 0x00 on VCC POR, VTR POR, SOFT RESET and PCI RESET
0x21 R
A read only register which provides device revision information. Bits[7:0] = current revision when read.
0x22 R/W
Bit[0] FDC Power Bit[1] Reserved Bit[2] Game Port Power Bit[3] Parallel Port Power Bit[4] Serial Port 1 Power Bit[5] Serial Port 2 Power Bit[6] MPU-401 Power Bit[7] Reserved 0: Power Off or Disabled 1: Power On or Enabled
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REGISTER Power Mgmt
ADDRESS 0x23 R/W
Default = 0x00 on VCC POR, VTR POR and PCI RESET
DESCRIPTION Bit[0] FDC (See Note in the Management" section) Bit[1] Reserved Bit[2] Reserved Bit[3] Parallel Port Bit[4] Serial Port 1 Bit[5] Serial Port 2 Bit[6] MPU-401 Bit[7] Reserved (read as 0)
"FDC
Power
OSC Default = 0x44, on on VCC POR, VTR POR and PCI RESET
0x24 R/W
For each bit above (except Reserved) = 0 Intelligent Pwr Mgmt off = 1 Intelligent Pwr Mgmt on Bit[0] Reserved Bit [1] PLL Control = 0 PLL is on (backward Compatible) = 1 PLL is off Bits[3:2] OSC = 01Osc is on, BRG clock is on. = 10Same as above (01) case. = 00Osc is on, BRG Clock Enabled. = 11Osc is off, BRG clock is disabled. Bit [5:4] Reserved, set to zero Bit [6] 16-Bit Address Qualification = 0 12-Bit Address Qualification = 1 16-Bit Address Qualification Note: For normal operation, bit 6 should be set. Bit[7] Reserved Reserved - Writes are ignored, reads return 0. Bit[7:1] Configuration Address Bits [7:1] Bit[0] = 0 See Note 1
Chip Level Vendor Defined Configuration Address Byte 0 Default =0x2E (Sysopt=0) =0x4E (Sysopt=1) on VCC POR and PCI RESET Configuration Address Byte 1 Default = 0x00 on VCC POR and PCI RESET Default = 0x00 on VCC POR, SOFT RESET and PCI RESET Chip Level Vendor Defined
0x25 0x26
0x27
Bit[7:0] Configuration Address Bits [15:8] See Note 1
0x28
Bits[7:0] Reserved - Writes are ignored, reads return 0.
0x29
Reserved - Writes are ignored, reads return 0.
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REGISTER TEST 6
ADDRESS 0x2A R/W
DESCRIPTION Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
Default = 0x00, on VCC POR and VTR POR TEST 4 Default = 0x00, on VCC POR and VTR POR TEST 5 Default = 0x00, on VCC POR and VTR POR
0x2B R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2C R/W
TEST 1 Default = 0x00, on VCC POR and VTR POR TEST 2 Default = 0x00, on VCC POR and VTR POR TEST 3 Default = 0x00, on VCC POR and VTR POR
0x2D R/W
Bit[7] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Bit[6] 8042 Reset: 1 = put the 8042 into reset 0 = take the 8042 out of reset Bits[5:0] Test Mode: Reserved for SMSC. Users should not write to this bit, may produce undesired results. Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2E R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
0x2F R/W
Test Modes: Reserved for SMSC. Users should not write to this register, may produce undesired results.
Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved to the specified location with no delay (Write byte 0, then byte 1; writing CR27 changes the base address).
The configuration address is only reset to its default address upon a PCI Reset or Vcc POR.
Note: The default configuration address is either 02Eh or 04Eh, as specified by the SYSOPT pin.
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9.4
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. This chip supports eight logical units and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard Controller, game port, Runtime Registers and MPU-401. A separate set (bank) of control and configuration registers exists for each logical device and is selected with the Logical Device # Register (0x07). The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the DATA PORT. The Logical Device registers are accessible only when the device is in the Configuration State. The logical register addresses are shown in the table below.
Table 66 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS (0x30) DESCRIPTION Bits[7:1] Reserved, set to zero. Bit[0] = 1 Activates the logical device currently selected through the Logical Device # register. = 0 Logical device currently selected is inactive
Activate (Note1) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET Logical Device Control Logical Device Control Memory Base Address I/O Base Address (Note 2) (see Device Base I/O Address Table) Default = 0x00 on VCC POR, VTR POR, PCI RESET and SOFT RESET Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note 3) on VCC POR, VTR POR, PCI RESET and SOFT RESET 0x72 = 0x00, on VCC POR, VTR POR, PCI RESET and SOFT RESET
(0x31-0x37) (0x38-0x3F) (0x40-0x5F) (0x60-0x6F) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0]
Reserved - Writes are ignored, reads return 0. Vendor Defined - Reserved - Writes are ignored, reads return 0. Reserved - Writes are ignored, reads return 0. Registers 0x60 and 0x61 set the base address for the device. If more than one base address is required, the second base address is set by registers 0x62 and 0x63. Refer to Table 67 for the number of base address registers used by each device. Unused registers will ignore writes and return zero when read.
(0x70,0x72)
0x70 is implemented for each logical device. Refer to Interrupt Configuration Register description. Only the keyboard controller uses Interrupt Select register 0x72. Unused register (0x72) will ignore writes and return zero when read. Interrupts default to edge high (ISA compatible).
(0x71,0x73)
Reserved - not implemented. These register locations ignore writes and return zero when read.
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LOGICAL DEVICE REGISTER
DMA Channel Select Default = 0x02 or 0x04 (Note 4) on VCC POR, VTR POR, PCI RESET and SOFT RESET 32-Bit Memory Space Configuration
ADDRESS (0x74,0x75)
DESCRIPTION Only 0x74 is implemented for FDC and Parallel port. 0x75 is not implemented and ignores writes and returns zero when read. Refer to DMA Channel Configuration.
(0x76-0xA8)
Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - not implemented. These register locations ignore writes and return zero when read. Reserved - Vendor Defined (see SMSC defined Logical Device Configuration Registers). Reserved
Logical Device
(0xA9-0xDF)
Logical Configuration Reserved
Device
(0xE0-0xFE)
0xFF
Note 1: A logical device will be active and powered up according to the following equation unless otherwise specified:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other.
Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O map, then read or write is not valid and is ignored. Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06. Note 4: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 and 5 is 0x04.
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LOGICAL DEVICE NUMBER 0x00
0x01 0x02 0x03
0x04
0x05
0x06 0x07
0x08 0x09
Table 67 - I/O Base Address Configuration Register Description BASE I/O FIXED LOGICAL RANGE REGISTER INDEX BASE OFFSETS DEVICE (Note 1) +0 : SRA FDC 0x60,0x61 [0x0100:0x0FF8] +1 : SRB +2 : DOR ON 8 BYTE BOUNDARIES +3 : TDR +4 : MSR/DSR +5 : FIFO +7 : DIR/CCR Reserved n/a n/a n/a Reserved n/a n/a n/a Parallel 0x60,0x61 [0x0100:0x0FFC] +0 : Data/ecpAfifo Port +1 : Status ON 4 BYTE BOUNDARIES +2 : Control (EPP Not supported) +400h : cfifo/ecpDfifo/tfifo/cnfgA or +401h : cnfgB [0x0100:0x0FF8] +402h : ecr ON 8 BYTE BOUNDARIES +3 : EPP Address (all modes supported, +4 : EPP Data 0 EPP is only available when the base address +5 : EPP Data 1 is on an 8-byte +6 : EPP Data 2 boundary) +7 : EPP Data 3 Serial Port 1 0x60,0x61 [0x0100:0x0FF8] +0 : RB/TB/LSB div +1 : IER/MSB div +2 : IIR/FCR ON 8 BYTE BOUNDARIES +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB/LSB div Serial Port 2 0x60,0x61 [0x0100:0x0FF8] +1 : IER/MSB div +2 : IIR/FCR ON 8 BYTE BOUNDARIES +3 : LCR +4 : MSR +5 : LSR +6 : MSR +7 : SCR Reserved n/a n/a n/a KYBD n/a Not Relocatable +0 : Data Register +4 : Command/Status Reg. Fixed Base Address: 60,64 Reserved n/a n/a n/a Game Port 0x60,0x61 [0x0100:0x0FFF] +00: Game Port Register on 1 byte boundaries
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Table 67 - I/O Base Address Configuration Register Description LOGICAL BASE I/O DEVICE LOGICAL RANGE FIXED REGISTER INDEX NUMBER DEVICE (Note 1) BASE OFFSETS 0x0A 0x60,0x61 [0x0000:0x0F7F] +00 : PME Status Runtime Register on 128-byte boundaries . Block . . +5F : Keyboard Scan Code (See Table in "Runtime Registers" section for Full List) 0x0B MPU-401 0x60,0x61 [0x0100:0x0FFE] +0: MIDI DATA on 2-byte boundaries +1: STATUS/COMMAND Config. Port 0x26, 0x27 0x0100:0x0FFE See Configuration Register in Table 64. Config. Accessed through the index and DATA Port (Note 2) On 2 byte boundaries ports located at the Configuration Port address and the Configuration Port address +1 respectively. Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration Register (CR24) must be set to `1' and Address Bits [A15:A12] must be `0' for 16 bit address qualification. Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can be relocated via the global configuration registers at 0x26 and 0x27. Table 68 - Interrupt Select Configuration Register Description NAME Primary Interrupt Select REG INDEX 0x70 (R/W) DEFINITION Bits[3:0] selects which interrupt is used for the primary Interrupt. 0x00= no interrupt selected 0x01= IRQ1 0x02= IRQ2/nSMI 0x03= IRQ3 0x04= IRQ4 0x05= IRQ5 0x06= IRQ6 0x07= IRQ7 0x08= IRQ8 0x09= IRQ9 0x0A= IRQ10 0x0B= IRQ11 0x0C= IRQ12 0x0D= IRQ13 0x0E= IRQ14 0x0F= IRQ15 Notes: All interrupts are edge high (except ECP/EPP) nSMI is active low
Default=0x00 or 0x06 (Note 1) on VCC POR, VTR POR, PCI RESET and SOFT RESET
Notes: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND: For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr. For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2 bit in the UART's Modem Control (MCR) Register. For the KYBD logical device (refer to the KYBD controller section of this spec). For MPU-401 logical device (refer to the MPU-401 section of this spec). IRQs are disabled if not used/selected by any Logical Device. Refer to Note A. nSMI must be disabled to use IRQ2. All IRQ's are available in Serial IRQ mode. Note 1: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
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Table 69 - DMA Channel Select Configuration Register Description NAME DMA Channel Select REG INDEX 0x74 (R/W) DEFINITION Bits[2:0] select the DMA Channel. 0x00= Reserved 0x01= DMA1 0x02= DMA2 0x03= DMA3 0x04-0x07= No DMA active
Default=0x02 or 0x04 (Note 1) on VCC POR, VTR POR, PCI RESET and SOFT RESET
Notes: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register. For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A. Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04. Note A: Logical Device IRQ and DMA Operation
1. IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ and DMA channel disabled by the Configuration Registers (active bit or address not valid). a) b) c) FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled. Digital Output Register (Base+2) bit D3 (DMAEN) set to "0". The FDC is in power down (disabled). Serial Ports: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt is disabled. Parallel Port: I. SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled. ii. ECP Mode: (1) (DMA) dmaEn from ecr register. See table. (2) IRQ - See table.
MODE (FROM ECR REGISTER) 000 PRINTER 001 SPP 010 FIFO 011 ECP 100 EPP 101 RES 110 TEST 111 CONFIG IRQ CONTROLLED BY IRQE IRQE (on) (on) IRQE IRQE (on) IRQE DMA CONTROLLED BY
dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn dmaEn
d) e)
Keyboard Controller: Refer to the KBD section of this spec. MPU-401: Refer to the MPU-401 section of this spec.
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9.5
SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers reset to their default values only on PCI resets generated by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by soft resets.
Table 70 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME FDD Mode Register REG INDEX DEFINITION 0xF0 R/W Bit[0] Floppy Mode =0 Normal Floppy Mode (default) =1 Enhanced Floppy Mode 2 (OS2) Bit[1] FDC DMA Mode =0 Burst Mode is enabled =1 Non-Burst Mode (default) Bit[3:2] Interface Mode = 11 AT Mode (default) = 10 (Reserved) = 01 PS/2 = 00 Model 30 Bit[4] FDC_SWAP 0 = Do Not Swap (default) 1 = Swap Drive 0 (nDS, nMTR pins) with Drive 1 (nDS, nMTR pins) Bit[5] Reserved, set to zero Bit[6] FDC Output Type Control =0 FDC outputs are OD12 open drain (default) =1 FDC outputs are O12 push-pull Bit[7] FDC Output Control =0 FDC outputs active (default) =1 FDC outputs tri-stated 0xF1 R/W Bit[0] Forced Write Protect =0 Inactive (default) =1 FDD nWRTPRT input is forced active when either of the drives has been selected.
Default = 0x0E on VCC POR, VTR POR and PCI RESET
FDD Option Register Default = 0x00 on VCC POR, VTR POR and PCI RESET
nWRTPRT (to the FDC Core) = WP (FDC SRA register, bit 1) = (nDS0 AND Forced Write Protect) OR (nDS1 AND Forced Write Protect) OR nWRTPRT (from the FDD Interface) OR Floppy Write Protect Note: The Floppy Write Protect bit is in the Device Disable register. Note: Boot floppy is always drive 0. Bit[1] Reserved Bits[3:2] Density Select = 00 Normal (default) = 01 Normal (reserved for users) = 10 1 (forced to logic "1") = 11 0 (forced to logic "0") Bit[7:4] Reserved.
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NAME FDD Type Register
Default = 0xFF on VCC POR, VTR POR and PCI RESET
FDD0 Default = 0x00 on VCC POR, VTR POR and PCI RESET
FDD1
REG INDEX DEFINITION 0xF2 R/W Bits[1:0] Floppy Drive A Type Bits[3:2] Floppy Drive B Type Bits[5:4] Reserved (could be used to store Floppy Drive C type) Bits[7:6] Reserved (could be used to store Floppy Drive D type) Note: The LPC47M192 supports two floppy drives 0xF3 R Reserved, Read as 0 (read only) 0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] Read as 0 (read only) Bits[4:3] Data Rate Table Select: DRT1, DRT0 Bits[5] Read as 0 (read only) Bits[6] Precompensation Disable PTS =0 Use Precompensation =1 No Precompensation Bits[7] Read as 0 (read only) 0xF5 R/W Refer to definition and default for 0xF4
Table 71 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME PP Mode Register REG INDEX DEFINITION 0xF0 R/W Bits[2:0] Parallel Port Mode = 100 Printer Mode (default) = 000 Standard and Bi-directional (SPP) Mode = 001 EPP-1.9 and SPP Mode = 101 EPP-1.7 and SPP Mode = 010 ECP Mode = 011 ECP and EPP-1.9 Mode = 111 ECP and EPP-1.7 Mode
Default = 0x3C on VCC POR, VTR POR and PCI RESET
Bit[6:3] ECP FIFO Threshold 0111b (default) Bit[7] PP Interupt Type Not valid when the parallel port is in the Printer Mode (100) or the Standard & Bi-directional Mode (000). = 1 Pulsed Low, released to high-Z. = 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,SPP, EPP] under ECP. IRQ level type when the parallel port is in ECP, TEST, or Centronics FIFO Mode. Bits[3:0] Reserved. Set to zero Bit [4] TIMEOUT_SELECT = 0 TMOUT (EPP Status Reg.) cleared on write of `1' to TMOUT. = 1 TMOUT cleared on trailing edge of read of EPP Status Reg. Bits[7:5] Reserved. Set to zero.
PP Mode Register 2 Default = 0x00 on VCC POR, VTR POR and PCI RESET
0xF1 R/W
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Table 72 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME Serial Port 1 Mode Register REG INDEX DEFINITION 0xF0 R/W Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled
Default = 0x00 on VCC POR, VTR POR and PCI RESET
Bit[1] High Speed = 0 High Speed Disabled(default) = 1 High Speed Enabled Bit[6:2] Reserved, set to zero Bit[7]: Share IRQ =0 UARTS use different IRQs =1 UARTS share a common IRQ See Note 1 below.
Note 1: To properly share and IRQ, 1. Configure UART1 (or UART2) to use the desired IRQ. 2. Configure UART2 (or UART1) to use No IRQ selected. 3. Set the share IRQ bit. Note: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs will assert when either UART generates an interrupt.
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UART Interrupt Operation Table Table 73 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME Serial Port 2 Mode Register REG INDEX DEFINITION 0xF0 R/W Bit[0] MIDI Mode = 0 MIDI support disabled (default) = 1 MIDI support enabled Default = 0x00 Bit[1] High Speed on VCC POR, = 0 High Speed disabled(default) VTR POR and = 1 High Speed enabled PCI RESET Bit[4:2] Reserved, set to zero Bit[5] TXD2_MODE (Note 1) Bit[5] reset on =0 The inactive state of the TXD2 pin is low. VTR POR only =1 The inactive state of the TXD2 pin is tristate. Bits[7:6] Reserved. Set to zero. IR Option Register 0xF1 R/W Bit[0] Receive Polarity = 0 Active High (Default) Default = 0x02 = 1 Active Low on VCC POR, Bit[1] Transmit Polarity VTR POR and = 0 Active High PCI RESET = 1 Active Low (Default) Bit[2] Duplex Select = 0 Full Duplex (Default) = 1 Half Duplex Bits[5:3] IR Mode = 000 Standard COM Functionality (Default) = 001 IrDA = 010 ASK-IR = 011 Reserved = 1xx Reserved Bit[6] IR Location Mux = 0 Use Serial port TXD2 and RXD2 (Default) = 1 Use alternate IRRX2 (pin 61) and IRTX2 (pin 62). Bit[7] Reserved, write 0. 0xF2 Bits [7:0] IR Half Duplex Timeout These bits set the half duplex time-out for the IR port. This value is 0 to 10msec in 100usec increments. Default = 0x03 0= blank during transmit/receive on VCC POR, 1= blank during transmit/receive + 100usec VTR POR and PCI RESET Note 1: The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only. Table 74 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME KRST_GA20 REG INDEX DEFINITION 0xF0 KRESET and GateA20 Select R/W Bit[7] Polarity Select for P12 = 0 P12 active low (default) = 1 P12 active high Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect MDAT signal to mouse wakeup (PME) logic.
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Default = 0x00 on VCC POR, VTR POR and PCI RESET
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DATASHEET
NAME REG INDEX DEFINITION 1=block mouse clock and data signals into 8042 Bits[6:5] reset on VTR POR only 0= do not block mouse clock and data signals into 8042 Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect KDAT signal to keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 Bit[4] MLATCH = 0 MINT is the 8042 MINT ANDed with Latched MINT (default) = 1 MINT is the latched 8042 MINT Bit[3] KLATCH = 0 KINT is the 8042 KINT ANDed with Latched KINT (default) = 1 KINT is the latched 8042 KINT Bit[2] Port 92 Select = 0 Port 92 Disabled = 1 Port 92 Enabled Bit[1] Reserved Bit[0] Reserved
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Table 75 - PME, Logical Device A [Logical Device Number = 0x0A] NAME CLOCKI32 REG INDEX DEFINITION 0xF0 Bit[0] (CLK32_PRSN) (R/W) 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded) Bit[1] SPEKEY_EN. This bit is used to turn the logic for the "wake on specific key" feature on and off. It will disable the 32kHz clock input to the logic when turned off. The logic will draw no power when disabled. 0= "Wake on specific key" logic is on (default) 1= "Wake on specific key" logic is off Bits[7:2] are reserved
Default = 0x00 on VTR POR
Note:
The registers located in Logical Device A are runtime registers.
Table 76 - MPU-401 [Logical Device Number = 0x0B] NAME REG INDEX DEFINITION MPU-401 Primary 0x60 R/W Bit[0] A8 Base I/O Address Bit[1] A9 High Byte Bit[2] A10 Bit[3] A11 Default = 0x03 Bit[4] "0" on PCI RESET, Bit[5] "0" SOFT RESET, VCC Bit[6] "0" POR and VTR POR Bit[7] "0" MPU-401 Primary 0x61 R/W Bit[0] "0" Base I/O Address Bit[1] A1 Low Byte Bit[2] A2 Bit[3] A3 Default = 0x30 Bit[4] A4 on PCI RESET, Bit[5] A5 SOFT RESET, VCC Bit[6] A6 POR and VTR POR Bit[7] A7 Note: Bit[0] must be "0".
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10 REGISTERS FOR HARDWARE MONITORING BLOCK
The registers in the Hardware Monitor Block may be accessed by writing the correct address to the 8-bit Internal Address Register.
10.1 Register Summary
REGISTER OFFSET (hex) 15-3D 3E 3F 40 41 42 47 49 4A 4B 4C 4F 50-59 TYPE DEFAULT REGISTER
W R/W R R R/W R R R/W R R/W R R/W R/W R/W
0x55 0x20 0x08 0x00 0x00 Note 1 Note 2 0x00 0x00 0x00 0x00 -
Internal Address Register Value or Limit Registers Company ID Stepping Number and Version Configuration Register Interrupt Status Register 1 Interrupt Status Register 2 VID Register VID 4 Register Test Mode Register Error Debug Register Test Digital Value Register Special Function Register Value or Limit Registers
Note 1: The default value on Bits[7:4]=0000 and Bits[3:0]=VID3 - VID0 Note 2: The default on Bits[7:1]=1000000 and Bit[0]=VID4
10.2 Internal Address Register
NAME Internal Address Register TYPE W DESCRIPTION This register is used to access the registers (see the following sub-sections). It stores the address of the register being accessed.
10.3 Value or Limit Registers (15h-3Dh)
REGISTER OFFSET (hex) 15 1E 1F 20 21 22 23 24 25 26 27 2B 2C
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TYPE
DESCRIPTION
DEFAULT
Read / Write Read/Write Read/Write Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read / Write Read / Write
Manufacturers Test Register (Not Implemented) Offset Register 2 Offset Register 1 +2.5V Reading Vccp Reading +3.3V Reading +5V Reading +12V Reading HVCC Reading Remote Diode Temperature Reading 1 Ambient Temperature Reading +2.5V High Limit +2.5V Low Limit
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NA 00h Note 1 00h Note 2 NA NA NA NA NA NA NA NA Note 3 Note 3
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REGISTER OFFSET (hex) 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3E-4F 50 51 52 53 54 55 56 57 58 59
TYPE
DESCRIPTION
DEFAULT
Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read/Write Read Only Read Only Read Only Read Only Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write
+Vccp High Limit +Vccp Low Limit +3.3V High Limit +3.3V Low Limit +5V High Limit +5V Low Limit +12V High Limit +12V Low Limit HVCC High Limit HVCC Sense Low Limit Remote Temperature High Limit 1 Remote Temperature Low Limit 1 Ambient Temperature High Limit Ambient Temperature Low Limit See the "Registers 3E-4F" subsection below +1.5V Reading +1.8V Reading Remote Diode Temperature Reading 2 Reserved +1.5V High Limit +1.5V Low Limit +1.8V High Limit +1.8V Low Limit Remote Temperature High Limit 2 Remote Temperature Low Limit 2
Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 NA NA NA 0x00 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3
Note 1: This offset register only applies to the remote diode temperature reading 2. This register contains a 2's complement value which is added (or subtracted if the number is negative) to external temperature reading 2. The default value in the offset register is zero, so initially zero is always added to the temperature reading. Note 2: This offset register only applies to the remote diode temperature reading 1. This register contains a 2's complement value which is added (or subtracted if the number is negative) to either the internal or external temperature reading. The default value in the offset register is zero, so initially zero is always added to the temperature reading. The offset register is configured for the external temperature channel by default. It may be switched to the internal channel by setting bit 4 of the Special Function Register to 1. Note 3: The default values of the High and Low limit registers should be written after power on reset.
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10.3.1.1
Registers 3Eh-4Fh REGISTER OFFSET (hex) 3E
NAME/DEFAULT
DESCRIPTION
Company ID Default=0x55 on HVCC POR and Initialization Stepping Number and Version Default=0x20 on HVCC POR and Initialization Configuration Default = 0x08 on HVCC POR and Initialization
Bits[7:0] This location contains the identification number which will be used by software to determine analog voltage curves.
(R)
3F (R)
Bits[7:0] This location contains the stepping number of the part in the lower four bits of the register [3:0]. The upper four bits reflect the Version Number [7:4]. The Hardware Monitor Block has a version number (Bits[7:4]) of 0010. For the A0 stepping of Hardware Monitor Block, this register will read 0010 0000. Bit[0] Start Logic 1 enables startup of monitor block, logic 0 places the block in the low power mode selected by bit 0 of the Special Function register at 4Fh. At startup, limit checking functions and scanning begins. Note, all HIGH and LOW LIMITS should be set into the ASIC prior to turning on this bit. Bits[3:1] Reserved Bit[4] Reset Setting this bit generates a minimum 20 ms low pulse on the Reset pin, if the function is enabled. (See VID Register). This bit is self-clearing. Bit[5] +12/VID4 Select Selects whether pin 10 acts as a 12 Volt Analog Input monitoring pin, or as a VID[4] input. This pin defaults to the 12 Volt Analog Input. Bit[6] Reserved Bit[7] Initialization Logic 1 restores powerup default values to the Configuration Register and Interrupt status registers. This bit automatically clears itself since the power on default is zero.
40 (R/WC) Bit[4] is self-clearing
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NAME/DEFAULT
Interrupt Status Register 1 Default = 0x00 on HVCC POR and Initialization
REGISTER OFFSET (hex) 41
DESCRIPTION
(R)
Interrupt Status Register 2 Default = 0x00 on HVCC POR and Initialization
42 (R)
Bit[0] +2.5v_Error A one indicates a High or Low limit has been reached or exceeded. Bit[1] Vccp_Error A one indicates a High or Low limit has been reached or exceeded. Bit[2] +3.3v_Error A one indicates a High or Low limit has been reached or exceeded. Bit[3] +5v_Error A one indicates a High or Low limit has been reached or exceeded. Bit[4] Ambient Temp Error A one indicates that a High or a Low temperature limit has been reached or exceeded. Bit[5] Remote Temp Error 1 A one indicates that a High or a Low temperature limit on the Remote Temperature limit has been reached or exceeded on D0+ and D0- pins. Bit[6] Remote Temp Error 2 A one indicates that a High or a Low temperature limit on the Remote Temperature limit has been reached or exceeded on D1+ and D1- pins. Bit[7] Reserved Bit[0] +12v_Error A one indicates a High or Low limit has been reached or exceeded. Bit[1] HVCC_Error A one indicates a High or Low limit has been reached or exceeded. Bit[2] +1.5v Error A one indicates a High or Low limit has been reached or exceeded. Bit[3] +1.8v Error A one indicates a High or Low limit has been reached or exceeded. Bits[5:4] Reserved Bit[6] Remote Diode Fault 1 A one indicates either a short or open circuited fault on the remote thermal diode inputs (D0+ and D0-). The following faults are detected: open D0+, open D0-, short to VCC on D0+, short to VCC on D0-, short to ground on D0+, short to ground on D0-, D0+ and D0- shorted to each other. Bit[7] Remote Diode Fault 2 A one indicates either a short or open circuited fault on the remote thermal diode inputs (D1+ and D1-). The following faults are detected: open D1+, open D1-, short to VCC on D1+, short to VCC on D1-, short to ground on D+, short to ground on D1-, D1+ and D1- shorted to each other.
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NAME/DEFAULT
VID Register Default: Bits[7:4]=0000 Bits[3:0]=VID3VID0 on HVCC POR and Initialization VID4 Register Default: Bits[7]=1, Bits[6:1]=0 Bit[0]=VID4 on HVCC POR and Initialization Test Mode Register Default = 0x00 on HVCC POR and Initialization
REGISTER OFFSET (hex) 47
DESCRIPTION
Bits[6:0] are Read Only; Bit[7] is (R/W)
49 (R)
Bits[3:0] VID[3:0] The VID[3:0] inputs from Pentium/PRO power supplies to indicate the operating voltage (e.g. 1.5V to 2.9V). Bits[6:4] Reserved Bit[7] RESET# Enable 0= Enables A0 pin for lowest order programmable bit of SMBus address (Default) 1= Enables the RESET# pin output function Bit[0] VID 4 VID 4 Input (If selected). Bits[6:1] Reserved Bit[7] Reserved1
4A (R/W)
Error Register
Debug
4B (R)
Default = 0x00 on HVCC POR and Initialization
Bit[0] selects the ADC test mode. The default for this bit is zero, which deactivates ADC test mode. Bit[1] selects the digital test mode. The default for this bit is zero, which deactivates digital test mode. Bit[2] selects the external clock test mode. The default for this bit is zero, which deactivates external oscillator clock test mode. Bit[3] selects either 8 or 1 averaging for the ADC test mode. The default for this bit is zero, which sets the averaging to 8 for the ADC test mode. A one in this bit selects no averaging. Bit[4] selects the oscillator clock to be muxed out on the VID2 pin. The default for this bit is zero, which deactivates mux oscillator clock test mode. Bits[7:5] are used by the analog block for test purposes. These three bits of register 4Ah are muxed out on pins dig_test_an_pad[2:0]. These bits are also used to mux out either the SDA line or the SCLK line to the VID3 pin. If bits[7:5] are `001', then the SDA line is muxed out onto the VID3 pin. If bits[7:5] are `010', then the SCLK line is muxed out onto the VID3 pin. Bit[0] indicates that no NACK was generated by the host during either a read byte protocol or a receive byte protocol. Bit[1] indicates a read or a write was attempted to an invalid register location. Bit[2] indicates a write to a read only register was attempted Bit[3] indicates a receive byte protocol was attempted when the address pointer register pointed to the 00h location. This is the default register location on power on reset. As noted in the "Bus Protocols" section of the "Hardware Monitoring Interface" section, the Internal Address register should be set up with a valid address location by either a send byte protocol or a write byte protocol after power-on-reset, before the receive byte protocol. Bit[4] indicates an invalid slave address was detected. Bit[5] indicates a premature stop was detected. Bit[6] indicates an error was detected during the SMBus Receive Byte Protocol Response to an ARA. Bit[7] is reserved.
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NAME/DEFAULT
Test Digital Value Register Default = 0x00 on HVCC POR and Initialization Special Function Register Default = 0x00 on HVCC POR and Initialization
REGISTER OFFSET (hex) 4C
DESCRIPTION
This register is used for the digital test mode test.
(R/W)
4F (R/W)
Bit[0] Low-Power Mode Select 0= Sleep Mode (default) 1= Shutdown Mode Bit[1] Monitoring Mode Select 0= Continuous Monitor Mode (default) 1= Cycle Monitor Mode Bit[2] THERM# Enable 0=A0/RESET function as selected by bit 7 of VID register (default) 1=Enables THERM# pin output function Bit[3] THERM# Voltage Enable 0=Out-of-limit/equal-limit voltages do not affect the state of the THERM# pin (default) 1=Enable out-of-limit/equal-limit voltages to make the THERM# pin active low Bit [4] Offset Register Configure
0= offset register configured to the external temperature channels. (Default) 1= offset register configured to the internal temperature channel.
Bit[5] Number of measurements of each temperature and voltage reading made. 0= take 128 separate measurements of the data from the analog block for both remote diode temperature readings before averaging the result and storing it in the value register for remote diode temperature measurements; take 8 separate measurements of all other voltage and internal temperature readings before averaging. (Default) 1 =use 16 averaging for both remote diode temperature readings and no averaging for all other voltage and internal temperature values. Setting this bit to `1' would be used for power saving. Bits[7:6] Reserved
Note: Reserved bits are Read-Only and return `0' when read. Reserved1 bits are Read-Only and return a `1' when read.
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11 OPERATIONAL DESCRIPTION 11.1 Maximum Guaranteed Ratings
Operating Temperature Range ................................................................................................................... 0oC to +70oC Storage Temperature Range ................................................................................................................... -55o to +150oC Lead Temperature Range ......................................................................................... Refer to JEDEC Spec. J-STD-020
Note: Stresses above those listed above and below could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
11.1.1 SUPER I/O SECTION (PINS 1 TO 100)
Maximum Vcc .......................................................................................................................................................... +5.5V Positive Voltage on any pin, with respect to Ground ..........................................................................................Vcc+0.3V Negative Voltage on any pin, with respect to Ground ............................................................................................. -0.3V
11.1.2 HARDWARE MONITORING BLOCK (PINS 101 TO 128)
Positive Supply Voltage (V+) Voltage on Any Input or Output Pin Voltage on the Voltage Channels +5.5 V (max) -0.3V to (HVcc+0.3V) (Except analog inputs) -0.3V to (Channel Voltage + 10%)
11.2 Hardware Monitoring Block Specifications
11.2.1 KEY SPECIFICATIONS
Supply Voltage Voltage monitoring accuracy Temperature Accuracy ADC Resolution HVcc-10% 11.2.2 SUPPLY CURRENT
Monitoring Mode Sleep Mode Shutdown Mode 1.2 mA (typical) 200 A (typical) 1 A (typical) 2 mA (max) 500 A (max) 3 A (max)
11.2.3 OPERATING TEMPERATURE
Operating Temperature Range 0 C <= TA <= +70 C
11.2.4 OPERATING VOLTAGE RATINGS
Supply Voltage (V+) VIN Voltage Range (Digital pins) 3.3 Volt Supply +3 V to +3.6 V -0.05 V to 3.6V
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11.3 DC Electrical Characteristics
SUPER I/O BLOCK
(TA = 0 C - 70 C, Vcc = +3.3 V 10%) PARAMETER SYMBOL I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis O6 Type Buffer Low Output Level High Output Level O8 Type Buffer Low Output Level High Output Level OD8 Type Buffer Low Output Level High Output Level O12 Type Buffer Low Output Level High Output Level OD12 Type Buffer Low Output Level High Output Level OD14 Type Buffer Low Output Level High Output Level OP14 Type Buffer Low Output Level High Output Level VILI VIHI
o
o
MIN
TYP
MAX
UNITS
COMMENTS
0.8 2.0 5.5
V V
TTL Levels
VILIS VIHIS VHYS 2.2 100
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
VOL VOH 2.4
0.4
V V
IOL = 6mA IOH = -3mA
VOL VOH 2.4
0.4
V V
IOL = 8mA IOH = -4mA
VOL VOH
0.4 Vcc+0.3
V V
IOL = 8mA Open Drain; Vcc=3.3V
VOL VOH 2.4
0.4
V V
IOL = 12mA IOH = -6mA
VOL VOH
0.4 Vcc+0.3
V V
IOL = 12mA Open Drain; Vcc=3.3V
VOL VOH
0.4 Vcc+0.3
V V
IOL = 14mA Open Drain; Vcc=3.3V
VOL VOH 2.4
0.4
V V
IOL = 14mA IOH = -14mA
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SUPER I/O BLOCK
(TA = 0 C - 70 C, Vcc = +3.3 V 10%) PARAMETER SYMBOL IO8 Type Buffer Low Input Level High Input Level Low Output Level High Output Level IS/O8 Type Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis Low Output Level High Output Level IO12 Type Buffer Low Input Level High Input Level Low Output Level High Output Level IOP14 Type Buffer Low Input Level High Input Level Low Output Level High Output Level IOD16 Type Buffer Low Input Level High Input Level Low Output Level High Output Level PCI Type Buffers (PCI_ICLK, PCI_I, PCI_IO)
SMSC DS - LPC47M192
o
o
MIN
TYP
MAX
UNITS
COMMENTS
VILI VIHI VOL VOH 2.4 2.0
0.8 5.5 0.4
V V V V
TTL Levels
IOL = 8mA IOH = -4mA
VILI VIHI VHYS VOL VOH 2.4 2.2 100
0.8 5.5
V V mV
Schmitt Trigger Schmitt Trigger
0.4
V V
IOL = 8mA IOH = -4mA
VILI VIHI VOL VOH 2.4 2.0
0.8 5.5 0.4
V V V V
TTL Levels
IOL = 12mA IOH = -6mA
VILI VIHI VOL VOH 2.4 2.0
0.8 5.5 0.4
V V V V
TTL Levels
IOL = 14mA IOH = -14mA
VILI VIHI VOL VOH 3.3V PCI 2.1 Compatible. PCI_O,
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0.8 2.0 5.5 0.4 Vcc+0.3
V V V V
TTL Levels
IOL = 16mA Open Drain; Vcc=3.3V
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DATASHEET
SUPER I/O BLOCK
(TA = 0 C - 70 C, Vcc = +3.3 V 10%) PARAMETER SYMBOL Leakage Current (ALL) Input High Current Input Low Current Backdrive Protect/ChiProtect (All signal pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) Input High Current Input Low Current
5V Tolerant Pins (All signal pins excluding LAD[3:0], LDRQ#, LPCPD#, LFRAME#) Inputs and Outputs in High Impedance State
o
o
MIN
TYP
MAX
UNITS
COMMENTS (Note 1)
ILEAKIH ILEAKIL
10 -10
A A
VIN = VCC VIN = 0V
ILEAKIH ILEAKIL
10 -10
A A
VCC = 0V VIN = 5.5V Max VIN = 0V
Input High Current Input Low Current
LPC Bus Pins (LAD[3:0], LDRQ#, LPCPD#, LFRAME#)
ILEAKIH ILEAKIL
10 -10
A A
VCC = 0V VIN = 5.5V Max VIN = 0V
Input High Current Input Low Current
VCC Supply Current Active
ILEAKIH ILEAKIL ICC
10 -10 15 (Note 2) VCC min -.5V (Note 2) 0.25 (Note 3) VCC max
A A mA
VCC = 0V and VCC = 3.3V VIN = 3.6V Max VIN = 0V All outputs open, all inputs transitioning from/to 0V to/from 3.3V. VCC must not be greater than .5V above VTR All outputs, all inputs transitioning from/to 0V to/from 3.3V. VREF can be either 3.3V (nominal) or 5V (nominal)
Trickle Supply Voltage
VTR
V
VTR Supply Current Active
ITR
5 (Note 3) 5.5 1
mA
Reference Voltage VREF Supply Current Active
VREF IREF
V mA
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HARDWARE MONITORING BLOCK
(TA = 0 C - 70 C, HVCC = +3.3 10%) PARAMETER SYMBOL Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy
o
o
MIN
TYP
MAX
UNITS
COMMENTS
-3 -2 1
+3 +2
o o
C C o C
00C <= TA <= 700C 400C <= TA <= 700C Resolution
External Accuracy
Diode
Sensor -5 -3 1 +5 +3
o o
C C o C
-400C <= TS <= 1250C 400C <= TS <= 1000C Resolution
Remote Source Current High Level Low Level
Analog-to-Digital Converter Characteristics
90 5.5
130 7.5
A A
Total Unadjusted Error Differential Non-Linearity Power Supply Sensitivity Total Monitoring Cycle Time (Cycle Mode) Conversion Time (Continuous Mode) Option 1 Option 2 Input Resistance ADC Resolution
IM Type Input Buffer (A0, VID0-VID4, XNOR_IN)
TUE DNL PSS tC(Cycle) 1 1 1.0
2
% LSB %/V
Note 4
1.4
sec
Note 5
Note 6 tC(Cts) tC(Cts) 542.336 67.792 140 200 msec msec k 8 bits
Low Input Level High Input Level IM Type Input Buffer (SCLK) Low Input Level High Input Level Hysteresis
VILI VIHI 2.1
0.8 HVcc+0.3
V V
VILI VIHI VHYS 2.1 500
0.8 HVcc+0.3
V V mV
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HARDWARE MONITORING BLOCK (TA = 0oC - 70oC, HVCC = +3.3 10%) PARAMETER SYMBOL MIN TYP MAX UNITS Temperature-to-Digital Converter Characteristics
COMMENTS
Internal Temperature Accuracy
-3 -2 1
+3 +2
o o
C C o C
00C <= TA <= 700C 400C <= TA <= 700C Resolution
External Accuracy
Diode
Sensor -5 -3 1 +5 +3
o o
C C o C
0 0 -40 C <= TS <= 125 C 0 0 40 C <= TS <= 100 C Resolution
Remote Source Current High Level Low Level
IMO3 Type Buffer (A0/RESET#/THERM#/ XNOR_OUT)
90 5.5
130 7.5
A A Note 7
Low Input Level High Input Level Low Output Level High Output Level RESET# Pulse Width IMOD3 Type Buffer (SDA) Low Input Level High Input Level Hysteresis Low Output Level High Output Level Leakage Current (ALL - Digital) Input High Current Input Low Current Digital Input Capacitance
VILI VIHI VOL VOH tReset_PW 2.4 20 2.1
0.8 HVcc+0.3 0.4 HVcc+0.3 45
V V V V msec IOL = +3.0 mA IOH = -3.0 mA HVCC = 3.3 V
VILI VIHI VHYS VOL VOH 2.1 500
0.8 HVcc+0.3
V V mV
0.4 HVcc+0.3
V V
IOL = +3.0 mA Open Drain, HVCC = 3.3 V (Note 1)
ILEAKIH ILEAKIL CIN
10 -10 10
A A pF
VIN = VCC VIN = 0V
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HARDWARE MONITORING BLOCK
(TA = 0 C - 70 C, HVCC = +3.3 10%) PARAMETER SYMBOL Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy
o
o
MIN
TYP
MAX
UNITS
COMMENTS
-3 -2 1
+3 +2
o o
C C o C
00C <= TA <= 700C 400C <= TA <= 700C Resolution
External Accuracy
Diode
Sensor -5 -3 1 +5 +3
o o
C C o C
-400C <= TS <= 1250C 400C <= TS <= 1000C Resolution
Remote Source Current High Level Low Level
130 90 A 7.5 5.5 A IANG Type Buffer - Analog Refer to "Appendix A - Thermal Diode Parameters" and "Appendix B - ADC Inputs Voltage Conversion". (Dx+, Dx-, +2.5V_IN, +3.3V_IN, +5V_IN, +12V_IN) VCC Supply Current Active See "Supply Current" subsection in "Hardware Monitoring Block Specifications" section above.
Notes:
Voltages are measured from the local ground potential, unless otherwise specified. Typicals are at TA=25C and represent most likely parametric norm. The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / QJA. Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V.
Note 1: All leakage currents are measured with all pins in high impedance. Note 2: The minimum value given for VTR applies when VCC is active. When VCC is 0V, the minimum VTR is 0V. Note 3: Max ITRI with VCC = 3.3V (nominal) is 5mA Max ITRI with VCC = 0V (nomial) is 250uA Note 4: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Note 5: Total Monitoring Cycle Time includes all temperature conversions, all analog input voltage conversions. Note 6: The cycle time for option 1 is 542.336ms (typical) if 128 measurements are averaged for the remote diode temperature reading and 8 measurements are averaged for all voltage and the internal temperature reading. It is 67.792ms (typical) for option 2 if 16 measurements are averaged for the remote diode temperature reading and a single measurement is taken for all voltage and the internal temperature reading (i.e., no averaging). Note 7: VOH min and IOH does not apply to the RESET# and THERM# open-drain functions.
11.3.1 CAPACITANCE VALUES FOR PINS
The input and output capacitance applies to both the Super I/O Block and the Hardware Monitoring Block digital pins.
CAPACITANCE TA = 25oC; fc = 1MHz; VCC = 3.3V 10% PARAMETER Clock Input Capacitance SYMBOL CIN MIN LIMITS TYP MAX 20 UNIT pF TEST CONDITION All pins except pin under test tied to AC ground
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
Note: The input capacitance of a port is measured at the connector pins.
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12 TIMING DIAGRAMS
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
CAPACITANCE TOTAL (pF)
NAME SER_IRQ LAD# [3:0] LDRQ# nDIR nSTEP nDS0 nDS1 PD[0:7] nSTROBE nALF J1X-Y J2X-Y KDAT KCLK MDAT MCLK MIDI_Tx FANx LEDx TXD1 TXD2 SDA
50 50 50 240 240 240 240 240 240 240 50 50 240 240 240 240 50 50 50 50 50 240
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t1 V cc
t2 t3
A ll H o s t A ccesses
FIGURE 12 - POWER-UP TIMING NAME DESCRIPTION MIN TYP MAX UNITS
t1 t2 t3
Vcc Slew from 2.7V to 0V Vcc Slew from 0V to 2.7V All Host Accesses After Powerup (Note 1)
300 100 125 500
us us us
Note 1: Internal write-protection period after Vcc passes 2.7 volts on power-up
t1
CLOCKI
t2
t2
FIGURE 13 - INPUT CLOCK TIMING NAME t1 t2 t1 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ MIN TYP 69.84 35 31.25 MAX UNITS ns ns s s ns
20
t2
Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown)
15.63 5
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t1
t4 t3 t2
P C I_ C L K
t5
FIGURE 14 - PCI CLOCK TIMING NAME t1 t2 t3 t4 t5 DESCRIPTION
Period High Time Low Time Rise Time Fall Time
MIN 30 12 12
TYP
MAX 33.3
3 3
UNITS nsec nsec nsec nsec nsec
PCI_RESET#
t1
FIGURE 15 - RESET TIMING NAME t1 DESCRIPTION
PCI_RESET# width
MIN 1
TYP
MAX
UNITS ms
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CLK t1 Output Delay t2 t3 Tri-State Output
FIGURE 16 - OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 CLK to Signal Valid Delay - Bused Signals t2 Float to Active Delay t3 Active to Float Delay MIN 2 2 TYP MAX 11 11 28 UNITS ns ns ns
t1 CLK Input
Inputs Valid
t2
FIGURE 17 - INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 Input Set Up Time to CLK - Bused Signals t2 Input Hold Time from CLK MIN 7 0 TYP MAX UNITS ns ns
PCI_CLK LFRAME# LAD[3:0]
L1 L2 Address Data TAR Sync=0110 L3 TAR
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 FIGURE 18 - I/O WRITE
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PCI_CLK LFRAME# LAD[3:0]
L1 L2 Address TAR Sync=0110 L3 Data TAR
Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 FIGURE 19 - I/O READ
PCI_CLK LDRQ#
Start MSB LSB ACT
FIGURE 20 - DMA REQUEST ASSERTION THROUGH LDRQ#
PCI_CLK LFRAME# LAD[3:0]
Start C+D CHL Size TAR Sync=0101 L1 Data TAR
Note: L1=Sync of 0000 FIGURE 21 - DMA WRITE (FIRST BYTE)
PCI_CLK LFRAME# LAD[3:0]
Start C+D CHL Size Data TAR Sync=0101 L1 TAR
Note: L1=Sync of 0000 FIGURE 22 - DMA READ (FIRST BYTE)
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nDIR
t3
nSTEP t9 nDS0-1
t4 t1 t2
t5
nINDEX
t6
nRDATA
t7
nWDATA
t8
FIGURE 23 - FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after STEP# nSTEP Cycle Time nDS0 & nDS1 Hold Time from nSTEP Low (Note) nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0 & nDS1, Setup Time nDIR Low (Note) MIN TYP 4 24 96 132 20 2 40 .5 MAX UNITS X* X* X* X* X* X* ns Y* ns
0
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) Note: The DS0 &DS1 setup and hold times must be met by software.
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t1 nWRITE
t2
t3 PD<7:0> t4 t5 t6 nDATASTB nADDRSTB t8 nWAIT
FIGURE 24 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to nWRITE Change (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) PDATA Valid to Command Asserted nWRITE to Command Asserted nWAIT Asserted to Command Asserted (Note 1) nWAIT Deasserted to Command Deasserted (Note 1) Command Asserted to nWAIT Deasserted Command Deasserted to nWAIT Asserted MIN 60 60 0 10 5 60 60 TYP MAX 185 185 UNITS ns ns ns ns ns ns ns
t7
t9
35 210 190 10
t8 t9
0 0
us ns
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to have settled after it does not transition for a minimum of 50 nsec.
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t1 nWRITE t3 PD<7:0> t7 t8 t9 DATASTB ADDRSTB t11 nWAIT
FIGURE 25 - EPP 1.9 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION MIN TYP MAX
t2
t4
t5
t6
t10
t12
UNITS
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
nWAIT Asserted to nWRITE Deasserted nWAIT Asserted to nWRITE Modified (Notes 1,2) nWAIT Asserted to PDATA Hi-Z (Note 1) Command Asserted to PDATA Valid Command Deasserted to PDATA Hi-Z nWAIT Asserted to PDATA Driven (Note 1) PDATA Hi-Z to Command Asserted nWRITE Deasserted to Command nWAIT Asserted to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) PDATA Valid to nWAIT Deasserted PDATA Hi-Z to nWAIT Asserted
0 60 60 0 0 60 0 1 0 60 0 0
185 190 180
ns ns ns ns ns
190 30 195 180
ns ns ns ns ns ns s
Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. Note 2: When not executing a write cycle, EPP nWRITE is inactive high.
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t1 nWRITE t2 PD<7:0> t3 t4 nDATASTB nADDRSTB t5 nWAIT
FIGURE 26 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION MIN TYP MAX UNITS
t1 t2 t3 t4 t5
Command Deasserted to nWRITE Change Command Deasserted to PDATA Invalid PDATA Valid to Command Asserted nWRITE to Command Command Deasserted to nWAIT Deasserted
0 50 10 5 0
40 35 35
ns ns ns ns ns
nWRITE t1 PD<7:0> nDATASTB nADDRSTB t3 nWAIT
FIGURE 27 - EPP 1.7 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION MIN TYP MAX UNITS
t2
t1 t2 t3
Command Asserted to PDATA Valid Command Deasserted to PDATA Hi-Z Command Deasserted to nWAIT Deasserted
0 0 0
ns ns ns
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to FIGURE 28.
ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 29. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe).
Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has beed accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in FIGURE 30.
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs.
t6 t3 PD<7:0> t1 t2 t5
nSTROBE
t4 BUSY
FIGURE 28 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION MIN TYP MAX UNITS
t1 t2 t3 t4 t5 t6
PDATA Valid to nSTROBE Active nSTROBE Active Pulse Width PDATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1)
600 600 450 500 680 80
ns ns ns ns ns ns
Note 1: The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
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t3 nALF t4 PD<7:0> t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8
FIGURE 29 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION MIN TYP MAX UNITS
t1 t2 t3 t4 t5 t6 t7 t8
nALF Valid to nSTROBE Asserted PDATA Valid to nSTROBE Asserted BUSY Deasserted to nALF Changed (Notes 1,2) BUSY Deasserted to PDATA Changed (Notes 1,2) nSTROBE Asserted to Busy Asserted nSTROBE Deasserted to Busy Deasserted BUSY Deasserted to nSTROBE Asserted (Notes 1,2) BUSY Asserted to nSTROBE Deasserted (Note 2)
0 0 80 80 0 0 80 80
60 60 180 180
ns ns ns ns ns ns
200 180
ns ns
Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out. Note 2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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t2 PD<7:0> t1 t5 nACK t4 nALF
FIGURE 30 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION MIN TYP MAX UNITS
t6
t3
t4
t1 t2 t3 t4 t5 t6
PDATA Valid to nACK Asserted nALF Deasserted to PDATA Changed nACK Asserted to nALF Deasserted (Notes 1,2) nACK Deasserted to nALF Asserted (Note 2) nALF Asserted to nACK Asserted nALF Deasserted to nACK Deasserted
0 0 80 80 0 0 200 200
ns ns ns ns ns ns
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. Note 2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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DATA
0 t2 t1
1 t2
0
1
0
0
1
1
0
1
1
t1
IRRX n IRRX
Pa rame ter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 1 15kba ud Pul se Wid th at 57.6kba ud Pul se Wid th at 38.4kba ud Pul se Wid th at 19.2kba ud Pu lse Wi dth a t 9.6kba ud Pu lse Wi dth a t 4.8kba ud Pu lse Wi dth a t 2.4kba ud Bit Time at 1 15kba ud Bit Time at 57.6kba ud Bit Time at 38.4kba ud Bit Time at 19.2kba ud Bi t Ti me a t 9.6kba ud Bi t Ti me a t 4.8kba ud Bi t Ti me a t 2.4kba ud
min 1.4 1.4 1.4 1.4 1.4 1.4 1.4
ty p 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 1 04 2 08 4 16
m ax 2.71 3.69 5.53 1 1.07 2 2.13 4 4.27 8 8.55
units s s s s s s s s s s s s s s
No te s: 1. Recei ve Pu lse Detection C ri te ria: A re ceived p ulse is consi dered d etecte d if the receive d p ulse is a mini mum o f 1.41s. 2. IR RX: L5, CRF1 Bit 0 = 1 nIRRX: L5, CRF1 Bi t 0 = 0 (defaul t)
FIGURE 31 - IRDA RECEIVE TIMING
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DAT A
0 t2 t1
1
0
1
0
0
1
1
0
1
1
t2
t1
IRT X n IRT X
Parameter t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 Pulse Width at 115kbaud Pulse Widt h at 57. 6kbaud Pulse Widt h at 38. 4kbaud Pulse Widt h at 19. 2kbaud Pulse Widt h at 9. 6kbaud Pulse Widt h at 4. 8kbaud Pulse Widt h at 2. 4kbaud Bit T ime at 115kbaud Bit Time at 57.6kbaud Bit Time at 38.4kbaud Bit Time at 19.2kbaud Bit Tim e at 9.6kbaud Bit Tim e at 4.8kbaud Bit Tim e at 2.4kbaud
mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41
typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416
max 2.71 3.69 5.53 11.07 22.13 44.27 88.55
u nits s s s s s s s s s s s s s s
Notes: 1. IrDA @ 115k i s HPSIR com pati ble. IrDA @ 2400 wi ll al low compatibilit y with HP95LX and 48SX. 2. IRT X: L5, CRF 1 Bit 1 = 1 (default) nI RT X: L5, CRF1 Bit 1 = 0
FIGURE 32 - IRDA TRANSMIT TIMING
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DA A T 0 t1 IRRX n IRRX 1 t2 0 1 0 0 1 1 0 1 1
t3 M IRRX t5
t4
nM IRRX
t6
Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit Time M odu lated Outp ut " On" M odu lated Out put " Off" M odu lated Outp ut " On" M odu lated Out put " Off"
min
typ
max
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
Note s: 1 . IRRX: L 5, CRF 1 Bit 0 = 1 n IRRX: L5 , CRF 1 Bit 0 = 0 (de fault) M IRRX, nMI RRX are the mod ulate d ou tpu ts
FIGURE 33 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING
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DATA
0 t1
1 t2
0
1
0
0
1
1
0
1
1
IRTX n IRT X
t3 MIRTX t5 n MIRT X
t4
t6
Pa ramet er t1 t2 t3 t4 t5 t6 M odu lated Out put Bit T ime Off Bit T ime M odu lated Outp ut " On" M odu lated Outp ut " Off" M odu lated Outp ut " On" M odu lated Outp ut " Off"
min
t yp
max
units s s
0.8 0.8 0.8 0.8
1 1 1 1
1.2 1.2 1.2 1.2
s s s s
Note s: 1 . IRT X : L5 , CRF 1 Bit 1 = 1 (def ault) nI RTX: L 5, CRF1 Bit 1 = 0 MIRTX, nM IRTX a re the mod ulate d ou tpu ts
FIGURE 34 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING
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PCI_CLK t1 SER_IRQ
FIGURE 35 - SETUP AND HOLD TIME NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec
t2
Data Start TXD1, 2 Data (5-8 Bits) t1 Parity Stop (1-2 Bits)
FIGURE 36 - SERIAL PORT DATA NAME t1 DESCRIPTION Serial Port Data Bit Time MIN TYP tBR1 MAX UNITS nsec
Note 1: tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the "Baud Rate" table in the "Serial Port" section.
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VREF
2 VREF +/- 5% 3
J1X, J1Y, J2X, J2Y t1
FIGURE 37 - JOYSTICK POSITION SIGNAL NAME t1 DESCRIPTION Rise Time to 2/3 VREF MIN 20 TYP MAX UNITS sec
J1B1, J1B2, J2B1, J2B2
90% 10%
90% 10%
t1
FIGURE 38 - JOYSTICK BUTTON SIGNAL NAME t1, t2 DESCRIPTION Button Fall/Rise Time MIN
t2
TYP
MAX 10
UNITS sec
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KCLK/ MCLK t1
CLK CLK 1 2 t3 t4
t2 t6
CLK 9
CLK 10
CLK 11 t5
KDAT/ Start Bit MDAT
Bit 0
Bit 7
Parity Bit
Stop Bit
FIGURE 39 - KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME t1 DESCRIPTION Time from DATA transition to falling edge of CLOCK (Receive) Time from rising edge of CLOCK to DATA transition (Receive) Duration of CLOCK inactive (Receive/Send) Duration of CLOCK active (Receive/Send) Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) MIN 5 TYP MAX 25 UNITS sec
t2 t3 t4 t5 t6
5 30 30 >0 5
T4-5 50 50 50 25
sec sec sec sec sec
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Data
Idle (No Data) Start Bit t1
Idle (No Data) Stop Bit Data
MIDI_Tx
FIGURE 40 - MIDI DATA BYTE NAME t1 DESCRIPTION MIN 31.7 TYP 32 MAX 32.3 UNITS sec
MIDI Data Bit Time
Note: The MIDI bit clock is 31.25kHz +/- 1%
t1 FANx t2
FIGURE 41 - FAN OUTPUT TIMING NAME t1 t2 DESCRIPTION PWM Period (Note 1) PWM High Time (Note 2) MIN 0.021 0.00033 TYP MAX 25.5 25.1 UNITS msec msec
Note 1: The period is 1/fout,where fout is programmed through the FANx and Fan Control registers. The tolerance on fout is +/- 2%. Note 2: When Bit 0 of the FANx registers is 0, then the duty cycle is programmed through Bits[6:1] of these registers. If Bits[6:1] = "000000" then the FANx pin is low. The duty cycle is programmable through Bits[6:1] to be between 1.56% and 98.44%. When Bit 0 is 1, the FANx pin is high.
t1 t2 FAN_TACHx
FIGURE 42 - FAN TACHOMETER INTPUT TIMING NAME t1 t2 t3 DESCRIPTION Pulse Time (1/2 Revolution Time=30/RPM) Pulse High Time Pulse Low Time MIN 4tTACH1 3tTACH1 tTACH TYP MAX UNITS sec sec sec
t3
Note 1: tTACH is the clock used for the tachometer counter. programmed in the Fan Control register.
It is 30.52 * DVSR, where the divisor (DVSR) is
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t1 t2 LEDx
FIGURE 43 - LED OUTPUT TIMING NAME t1 t2 DESCRIPTION MIN 1 0 TYP MAX 2 0.51 UNITS sec sec
Period Blink ON Time
Note 1: The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01 indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink at 1/2 Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON.
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SMBus Timing
tLOW SCLK tHD;STA tHD;DAT tSU;STA tSU;STO tR tF tHD;STA
tHIGH
tSU;DAT
SDA tBUF P S S P
FIGURE 44 - SMBUS TIMING SYMBOL PARAMETER LIMITS MIN MAX 10 400 50 1.3 UNITS COMMENTS
SMB Operating Frequency kHz Note 1 Spike Suppression ns Note 2 Bus free time between Stop and Start s Condition THD:STA Hold time after (Repeated) Start 0.6 s Condition. After this period, the first clock is generated. TSU:STA Repeated Start Condition setup time 0.6 s TSU:STO Stop Condition setup time 0.6 s THD:DAT Data hold time 0.3 0.9 s TSU:DAT Data setup time 100 ns Note 3 TLOW Clock low period 1.3 s THIGH Clock high period 0.6 s TF Clock/Data Fall Time 20+0.1Cb 300 ns TR Clock/Data Rise Time 20+0.1Cb 300 ns Cb Capacitive load for each bus line 400 pF Note 1: The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum clock frequency for fast mode devices on the I2C bus. See "The I2C Bus Specification," version 2.0, Dec. 1998. Note 2: At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. Note 3: If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (TR max) + 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.
FSMB TSP TBUF
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13 PACKAGE OUTLINE
FIGURE 45 - 128 PIN QFP PACKAGE OUTLINE, 14x20x2.7 BODY, 3.2 MM FOOTPRINT MIN ~ 0.05 2.55 23.00 19.90 17.00 13.90 0.09 0.73 ~ NOMINAL ~ ~ ~ 23.20 20.00 17.20 14.00 ~ 0.88 1.60 0.50 Basic ~ ~ ~ ~ ~ MAX 3.4 0.5 3.05 23.40 20.10 17.40 14.10 0.20 1.03 ~ REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
A A1 A2 D D1 E E1 H L L1 e W R1 R2 ccc
0o 0.10 0.08 0.08 ~
7o 0.30 ~ 0.30 0.08
Notes: 1 Controlling Unit: millimeter. 2 Tolerance on the position of the leads is 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated.
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14 APPENDIX A - THERMAL DIODE PARAMETERS
The Pentium II and Pentium III processors incorporate an on-die diode that may be used to monitor the die temperature (junction temperature). The following table provides the diode parameters.
Table 77 - Thermal Diode Parameters SYMBOL I2 forward bias MIN 5 5 1.0000 1.0057 TYP MAX 500 300 1.0173 1.0125 UNIT uA uA NOTES 1 6 2, 3, 4 2, 3, 5, 6
n_ideality
1.0065 1.0080
Notes: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. At room temperature with a forward bias of 630 mV. 3. n_ideality is the diode ideality factor parameter, as represented by the diode equation: I2=I1(e^ (Vd*q)/(nkT) - 1) where I1 is saturation current Vd is change in Vbe q is the electron charge K is the Boltzmann's constant T is the absolute temperature in oK 4. This specification applies to the Pentium II processor and Pentium III processor (CPUID=067xh) for the SC242 at 450MHz to 1.13GHz. 5. This specification applies to the Pentium III processor (CPUID=068xh) for the SC242 at 450MHz to 1.13GHz. 6. This specification applies to the Pentium III processor for the PGA370 socket at 500MHz to 1GHz.
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15 APPENDIX B - ADC VOLTAGE CONVERSION
Table 78 - Analog-to-Digital Conversions for Hardware Monitoring Block
Input Voltage 12 VIN 5 VIN VCC/3.3 VIN 2.5 VIN 1.8 VIN 1.5 VIN VCCPIN A/D Output Decimal Binary
<0.062 0.062-0.125 0.125-0.188 0.188-0.250 0.250-0.313 0.313-0.375 0.375-0.438 0.438-0.500 0.500-0.563 ... 4.000-4.063 ... 8.000-8.063 ... 12.000-12.063 ... 15.312-15.375 15.375-15.437 15.437-15.500 15.500-15.563 15.625-15.625 15.625-15.688 15.688-15.750 15.750-15.812 15.812-15.875 15.875-15.938 >15.938
<0.026 0.026-0.052 0.052-0.078 0.078-0.104 0.104-0.130 0.130-0.156 0.156-0.182 0.182-0.208 0.208-0.234 ... 1.666-1.692 ... 3.330-3.560 ... 5.000-5.026 ... 6.380-6.406 6.406-6.432 6.432-6.458 6.458-6.484 6.484-6.510 6.510-6.536 6.536-6.562 6.562-6.588 6.588-6.615 6.615-6.640 >6.640
<0.0172 0.017-0.034 0.034-0.052 0.052-0.069 0.069-0.086 0.086-0.103 0.103-0.120 0.120-0.138 0.138-0.155 ... 1.100-1.117 ... 2.200-2.217 ... 3.300-3.317 ... 4.210-4.230 4.230-4.245 4.245-4.263 4.263-4.280 4.280-4.300 4.300-4.314 4.314-4.330 4.331-4.348 4.348-4.366 4.366-4.383 >4.383
<0.013 0.013-0.026 0.026-0.039 0.039-0.052 0.052-0.065 0.065-0.078 0.078-0.091 0.091-0.104 0.104-0.117 ... 0.833-0.846 ... 1.667-1.680 ... 2.500-2.513 ... 3.190-3.203 3.203-3.216 3.216-3.229 3.229-3.242 3.242-3.255 3.255-3.268 3.268-3.281 3.281-3.294 3.294-3.307 3.307-3.320 >3.320
<0.009 0.009-0.019 0.019-0.028 0.028-0.038 0.038-0.047 0.047-0.056 0.056-0.066 0.066-0.075 0.075-0.084 ... 0.600-0.609 ... 1.200-1.209 ... 1.800-1.809 ... 2.297-2.306 2.306-2.316 2.316-2.325 2.325-2.334 2.334-2.344 2.344-2.353 2.353-2.363 2.363-2.372 2.372-2.381 2.381-2.391 >2.391
<0.008 0.008-0.016 0.016-0.023 0.023-0.031 0.031-0.039 0.039-0.047 0.047-0.055 0.055-0.063 0.063-0.070 ... 0.500-0.508 ... 1.000-1.008 ... 1.500-1.508 ... 1.914-1.922 1.922-1.930 1.930-1.938 1.938-1.945 1.945-1.953 1.953-1.961 1.961-1.969 1.969-1.977 1.977-1.984 1.984-1.992 >1.992
<0.012 0.012-0.023 0.023-0.035 0.035-0.047 0.047-0.058 0.058-0.070 0.070-0.082 0.082-0.093 0.093-0.105 ... 0.749-0.761 ... 1.499-1.511 ... 2.249-2.261 ... 2.869-2.881 2.881-2.893 2.893-2.905 2.905-2.916 2.916-2.928 2.928-2.940 2.940-2.951 2.951-2.964 2.964-2.975 2.975-2.987 >2.988
0 1 2 3 4 5 6 7 8 ... 64 (1/4 Scale) ... 128 (1/2 Scale) ... 192 (3/4 Scale) ... 245 246 247 248 249 250 251 252 253 254 255
0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 ... 0100 0000 ... 1000 0000 ... 1100 0000 ... 1111 0101 1111 0110 1111 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
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16 APPENDIX C - TEST MODE
The LPC47M192 provides board test capability through the implementation of two XNOR chains. One chain is dedicated to the Super I/O portion of the chip (pins 1 - 100) and the second chain is dedicated solely to the Hardware Monitoring Block (pins 101 - 128).
XNOR-Chain Test Mode XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly and test operations. See FIGURE 46 below. When the chip is in the XNOR chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the LPC47M192 pin functions are disconnected from the device pins, which all become input pins except for one output pin at the end of XNOR-Chain. The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the XNOR-Chain output pin.
I/O#1
I/O#2
I/O#3
I/O#n
XNor Out
FIGURE 46 - XNOR-CHAIN TEST STRUCTURE
16.1 Super I/O Block
16.1.1 BOARD TEST MODE
Board test mode can be entered as follows: On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low. Exit board test mode as follows: On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high. See the "XNOR-Chain Test Mode" section above for a description of this board test mode. The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is 85, TXD1. See the following subsections for more details.
Pin List of Super I/O XNOR Chain Pins 1 to 100 on the chip are inputs to the first XNOR chain, with the exception of the following:
1. 2. 3. 4.
VCC (pins 53, 65, & 93), VTR (pin 18), and VREF (pin 44). VSS (pins 7, 31, 60, & 76) and AVSS (pin 40). TXD1 (pin 85) This is the chain output. nPCI_RESET (pin 26).
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To put the chip in the first XNOR chain test mode, tie LAD0 (pin 20) and LFRAME# (pin 24) low. Then toggle PCI_RESET# (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 20) and LFRAME# (pin 24) become part of the chain. To exit the first XNOR chain test mode tie LAD0 (pin 20) or LFRAME# (pin 24) high. Then toggle PCI_RESET# (pin 26) from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe the output at TXD1 (pin 85). Toggling any of the input pins in the chain should not cause its state to change.
Setup of Super I/O XNOR Chain Warning: Ensure power supply is off during setup. 1. Connect VSS (pins 7, 31, 60, & 76) and AVSS (pin 40) to ground. 2. Connect VCC (pins 53, 65, & 93), VTR (pin 18), and VREF (pin 44) to VCC (3.3V). 3. Connect an oscilloscope or voltmeter to TXD1 (pin 85). 4. All other pins should be tied to ground. Testing 1. Turn power on. 2. With LAD0 (pin 20) and LFRAME# (pin 24), low, bring PCI_RESET# (pin 26) high. The chip is now in XNOR chain test mode. At this point, all inputs to the first XNOR chain are low. The output, on TXD1 (pin 85), should also be low. Refer to INITIAL CONFIG on TRUTH TABLE 1. 3. Bring pin 100 high. The output on TXD1 (pin 85) should go high. Refer to STEP ONE on TRUTH TABLE 1. 4. In descending pin order, bring each input high. The output should switch states each time an input is toggled. Continue until all inputs are high. The output on TXD1 should now be low. Refer to END CONFIG on TRUTH TABLE 1. 5. The current state of the chip is now represented by INITIAL CONFIG in TRUTH TABLE 2. 6. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all inputs are low. The output on TXD1 should now be low. Refer to TRUTH TABLE 2. 7. To exit test mode, tie LAD0 (pin 20) OR LFRAME# (pin 24) high, and toggle PCI_RESET# from a low to a high state. TRUTH TABLE 1 - Toggling Inputs in Descending Order PIN 100 L PIN 99 L PIN 98 L PIN 97 L PIN 96 L PIN ... L PIN 1 L OUTPUT PIN 85 L
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 ... STEP N END CONFIG
H H H H H ... H H
L H H H H ... H H
L L H H H ... H H
L L L H H ... H H
L L L L H ... H H
L L L L L ... H H
L L L L L ... L H
H L H L H ... H L
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TRUTH TABLE 2 - Toggling Inputs in Ascending Order PIN 1 H PIN 2 H PIN 3 H PIN 4 H PIN 5 H PIN ... H PIN 100 H OUTPUT PIN 85 L
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP N END CONFIG
L L L L L ... L L
H L L L L ... L L
H H L L L ... L L
H H H L L ... L L
H H H H L ... L L
H H H H H ... L L
H H H H H ... H L
H L H L H ... H L
16.2 Hardware Monitoring Block
16.2.1 BOARD TEST MODE
Board test mode for the Hardware Monitor Block is implemented as an XNOR-chain as described in the subsection below. The XNOR chain for the Hardware Monitor Block is self-contained within the Hardware Monitor Block. The XNOR chain for the rest of the chip is separate from the XNOR chain for the Hardware Monitor Block. Board test mode for the Hardware Monitoring Block can be entered by programming a `1' to the XNOR_IN pin at power-up. To exit the test mode, the XNOR_IN pin should be tied to `0' on the subsequent power up.
16.2.2 XNOR-CHAIN TEST MODE
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the XNOR-Chain output pin. The XNOR-Chain output is on A0/RESET#/THERM#/XNOR_OUT pin. VCC, GND and all the analog pins are not used as inputs for XNOR-Chain Test.
Testing 1. Program a `1' on XNOR_IN pin. Turn power on. The Hardware Monitor Block is now in XNOR chain test mode. At this point, all inputs to the XNOR chain are low. The output on A0/RESET#/THERM#/XNOR_OUT will also be high. Refer to INITIAL CONFIG on TRUTH TABLE 3. 2. Bring VID4 pin high. The output on A0/RESET#/THERM#/XNOR_OUT will go low. Refer to STEP ONE on TRUTH TABLE 3. 3. In descending pin order, bring each input high. The output will switch states each time an input is toggled. Continue until all inputs are high. The output on A0/RESET#/THERM#/XNOR_OUT will now be low. Refer to END CONFIG on TRUTH TABLE 3. 4. The current state of the Hardware Monitor Block is now represented by INITIAL CONFIG in TRUTH TABLE 4. 5. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all inputs are low. The output on A0/RESET#/THERM#/XNOR_OUT will now be high. Refer to TRUTH TABLE 4. 6. To exit test mode, tie the XNOR_IN pin low, and power down the Hardware Monitor Block. The Hardware Monitor Block will not be in test mode on the subsequent power-up.
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TRUTH TABLE 3 - Toggling inputs in descending order
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 END CONFIG
VID4 L H H H H H H H
VID3 L L H H H H H H
VID2 L L L H H H H H
VID1 L L L L H H H H
VID0 L L L L L H H H
SCLK L L L L L L H H
SDA L L L L L L L H
XNOR_OUT H L H L H L H L
TRUTH TABLE 4 - Toggling inputs in ascending order
INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 END CONFIG
SDA H L L L L L L L
SCLK H H L L L L L L
VID0 H H H L L L L L
VID1 H H H H L L L L
VID2 H H H H H L L L
VID3 H H H H H H L L
VID4 H H H H H H H L
XNOR_OUT L H L H L H L H
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17 APPENDIX D - REFERENCE DOCUMENTS
1. 2. 3. 4. 5. 6. 7. 8. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. Metalious ACPI/Manageability Specification, v1.0, Aril 30, 1999 Advanced Configuration and Power Interface Specification, v 1.0 SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts. 9. SMSC Application Note, AN 8-20: Using the Hardware Monitor Feature in SMSC Super I/O Devices. 10. SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC Floppy Disk Controllers.
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18 LPC47M192 REVISIONS
DATE REVISED 03/30/05
PAGE(S) 3
SECTION/FIGURE/ENTRY 1 - GENERAL DESCRIPTION; Features
220
FIGURE 45 - 128 PIN QFP PACKAGE OUTLINE, 14x20x2.7 BODY, 3.2 MM FOOTPRINT
CORRECTION Lead-free ordering information added. Updated Package Outline
07/25/02
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